• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
• /
• pp.2367-2370
• /
• 2003

A fast pattern classification algorithm with Cellular Parallel Processing Network-based dynamic programming is proposed. The Cellular Parallel Processing Networks is an analog parallel processing architecture and the dynamic programming is an efficient computation algorithm for optimization problem. Combining merits of these two technologies, fast Pattern classification with optimization is formed. On such CPPN-based dynamic programming, if exemplars and test patterns are presented as the goals and the start positions, respectively, the optimal paths from test patterns to their closest exemplars are found. Such paths are utilized as aggregating keys for the classification. The pattern classification is performed well regardless of degree of the nonlinearity in class borders.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.1173-1176
• /
• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing cell array is proposed. It has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram. The constraints' length of trellis diagram is connected circularly so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• 대한전기학회논문지:시스템및제어부문D
• /
• 제52권11호
• /
• pp.650-656
• /
• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing ceil array Is proposed. The proposed Viterbi .decoder has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram, the output column of the analog processing cells is connected to the decoding column, and thus, the output(last) column becomes a column right before the decoding(first) column. The reference input signal given at a decoding column is propagated to the whole network while Its magnitude is reduced by the amount of a error metric on each branch. The circuit-based decoding is done by adding a trigger signals of same magnitudes to disconnect the path corresponding to logic 0 (or 1) and by observing its effect at an output column (the former column of the decoding column). The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• Applied Microscopy
• /
• 제46권1호
• /
• pp.6-13
• /
• 2016

Fluorescence lifetime imaging microscopy (FLIM) has been considered an effective technique to investigate chemical properties of the specimens, especially of biological samples. Despite of this advantageous trait, researchers in this field have had difficulties applying FLIM to their systems because acquiring an image using FLIM consumes too much time. Although analog mean-delay (AMD) method was introduced to enhance the imaging speed of commonly used FLIM based on time-correlated single photon counting (TCSPC), a real-time image reconstruction using AMD method has not been implemented due to its data processing obstacles. In this paper, we introduce a real-time image restoration of AMD-FLIM through fast parallel data processing by using Threading Building Blocks (TBB; Intel) and octa-core processor (i7-5960x; Intel). Frame rate of 3.8 frames per second was achieved in $1,024{\times}1,024$ resolution with over 4 million lifetime determinations per second and measurement error within 10%. This image acquisition speed is 184 times faster than that of single-channel TCSPC and 9.2 times faster than that of 8-channel TCSPC (state-of-art photon counting rate of 80 million counts per second) with the same lifetime accuracy of 10% and the same pixel resolution.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.289-289
• /
• 2010

Translation Characteristics of Digital Decoder utilizing the analog parallel processing circuit technology is designed. The fast parallel viterbi decoder system acted by a replacement of the conventional digital viterbi Decoder has good propagation. we are applied proposed analog viterbi decoder to decode PR signal for DVD and analyze the specific circuit and signal characteristics.

• 전기학회논문지
• /
• 제57권10호
• /
• pp.1888-1892
• /
• 2008

In this paper, a new parallel CMOS self-bias differential amplifier is designed to use in high-speed analog signal processing circuits. The designed parallel CMOS self-bias differential amplifier is developed by using internal biasing circuits and the complement gain stages which are parallel connected. And also, the parallel architecture of the designed parallel CMOS self-bias differential amplifier can improve the gain and gain-bandwidth product of the typical CMOS self-bias differential amplifier. With 1.8V $0.8{\mu}m$ CMOS process parameter, the results of HSPICE show that the designed parallel CMOS self-bias differential amplifier has a dc gain and a gain-bandwidth product of 64 dB and 49 MHz respectively.

• 한국인터넷방송통신학회논문지
• /
• 제9권1호
• /
• pp.39-45
• /
• 2009

본 논문에서는 최근 무선 통신 시스템에서 빠른 데이터전송 방식으로서 사용되고 있는 OFDM 통신방식의 저소비전력화 방안을 제안한다. 일반적으로 OFDM에서 주요 신호처리 방식은 디지털을 이용한 프리에 변환이다. 이런 디지털 프리에 변환은 많은 소비전력이 필요하며 이것은 무선통신 시스템에 있어서 커다란 제약이 되고 있다. 전류모드를 이용한 아날로그 프리에 변환(FFT) LSI는 이러한 소비전력의 문제를 해결할 수 있는 주요 대안으로 떠오르고 있다. 그러나 이러한 신호처리 방식을 사용하기 위해서는 전류모드를 이용한 직병렬/병직렬 변환기(Serial-to-Parallel/Parallel-to-Serial Converter)가 필수적으로 필요하다. 본 논문에서는 전류모드로 구성한 아날로그 프리에 변환(FFT) LSI를 이용해 수신단의 저소비전력을 실현하기 위해 필수적인 새로운 전류모드 직병렬/병직렬 변환기를 제시하였으며 설계된 칩의 측정결과가 시뮬레이션 결과와 일치하는 것을 확인하였다. 제안된 전류모드 직병렬/병직렬 변환기의 개발로 저소비전력에 큰 장점을 지니고 있는 아날로그 FFT LSI의 활용이 가능해졌으며 송수신단 시스템에서 큰 소비전력의 감소효과를 가져올 것으로 기대된다.

• 한국통신학회논문지
• /
• 제34권10A호
• /
• pp.776-783
• /
• 2009

본 논문에서는 OFDM과 같은 대용량 무선 전송방식의 베이스밴드단(Baseband) 신호처리 방식 중 직병렬/병직렬 변환기(Serial-to-Parallel/Parallel-to-Serial Converter)를 전류모드(Current-mode) 회로로 구현했을 경우 유효한 설계 기법을 제안한다. 전류모드를 이용한 OFDM(Orthogonal Frequency Division Multiplexing: 직교주파수분할다중)용 아날로그 프리에 변환(FFT) LSI의 병렬 입출력을 담당하는 전류모드 직병렬병직렬 변환기의 홀드모드(Hold mode)의 불필요한 전류를 제거할 수 있다. 이를 통해 전류모드로 구성한 아날로그 신호처리 시스템의 저소비전력을 실현하기 위해 필수적인 새로운 전류모드 직병렬/병직렬 변환기를 제시하고 설계된 칩의 측정결과가 시뮬레이션 결과와 일치하는 것을 확인하였다. 이를 통해 저전력형 대용량 무선통신 시스템의 베이스밴드단 구축이 가능한 전류모드 아날로그 시스템의 구현 가능성을 제시하였다.

• 대한전기학회논문지:시스템및제어부문D
• /
• 제54권11호
• /
• pp.643-649
• /
• 2005

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUD) sensors for precise MCG(MagnetoCardioGram) signal acquisitions. Such system needs to deal with hundreds of sensors, requiring fast signal sampling md precise analog-to-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit in 1 ks/s speed, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and specially designed parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 mili-second sampling interval. We extend the design into 256-channel hardware and analyze the speed .using the measured data from the 64-channel hardware. Since our design exploits full parallel processing, Assembly level coding, and NOP(No Operation) instruction for timing control, the design provides expandability and lowest system timing margin. Our result concludes that the data collection with 256-channel analog input signals can be done in 201.5us time-interval which is much shorter than the required 1 mili-second period.

• ETRI Journal
• /
• 제30권4호
• /
• pp.495-505
• /
• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.