• 한국초전도학회:학술대회논문집
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• v.11
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• pp.35-35
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• 2001

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.26-33
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• 2002

In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.3
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• pp.127-131
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• 1984

The IOVMM(Incoherent Optical Vector Matrix Multiplier) is constructed, which can process much information very fast by incogerent light source, and its experimental results are compared with the theoretical values. The input vector and matirx elements are limited to the positive number in this paper. The input vector is made by the LED array and the matrix is encoded on the film by the area modulation method. The result of the vector-matrix multiplication is detected by the photodiode array through the lens system. The analog multiplexer is used for looking at output signal on one channel.

• 전기의세계
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• v.9
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• pp.1-3
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• 1962

본고에서는 앞으로의 주된 연구과제인 원자로 Simulator로 쓰일 Repetitive형 Analog계산기의 multiplier용으로 사용하기 위하여, 간단하면서도 조정이 쉬우며 안정도와 신뢰도가 큰 삼극관을 사용한 Convertor 회로를 택하여 이를 실험 검토하는 한편 출력측의 cathode-follower진공관을 5751로 개변하여 우리 실정에 정합토록하였다. 즉 이렇게 하므로서 불필요한 소모전류를 절약하며 충분히 낮은 출력 impedance을 얻을 수 있고 또한 얻기에 용이하고 염가한 진공관을 사용하면서도 훌륭한 특성을 얻을 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1753-1758
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• 2012

This paper introduces analog FIR filters based on a distributed amplifier and analyzes the proposed filter's characteristics. A simple design method of an analog FIR filter based on the digital filter design technique is also introduced. The proposed analog FIR filters are a moving average(MA) and a comb type filters with no multiplier. This simple structures of the proposed filters may enable to operate at multi-GHz frequency range and applicable to combine a filter and an amplifier of RF system. The proposed analog FIR filters were implemented with standard $0.18{\mu}m$ CMOS technology. The designed GHz analog FIR filters are simulated by Cadence Spectre and compared to the results of digital FIR filters obtained from MATLAB simulations. From the simulation results, the characteristics of the proposed analog FIR filters are fairly well matched with those of digital FIR filters.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• ETRI Journal
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• v.39 no.2
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• pp.145-150
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• 2017

As wearable devices are powered by batteries, they need to consume as little energy as possible. To address this challenge, in this article, we propose a synergistic technique for energy-efficient approximate speech signal processing (ASSP) for wearable devices. More specifically, to enable the efficient trade-off between energy consumption and sound quality, we synergistically integrate an approximate multiplier and a successive approximate register analog-to-digital converter using our enhanced conversion algorithm. The proposed ASSP technique provides ~40% lower energy consumption with ~5% higher sound quality than a traditional one that optimizes only the bit width of SSP.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1315-1317
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• 2003

In this paper, a hew ground speed signal detector used for railway vehicles is presented. A frequency 6-multiplier is designed to the proposed speed signal detector to achieve more precise ground speed from the slow analog signals made from mechanical tacho signal generator. The computer simulation is carried out to clarify its effectiveness.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.189-192
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• 1991

This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.