• Electrical & Electronic Materials
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• v.16 no.9
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• pp.64.2-65
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• 2003

A 4 nm layer of ZrOx (targeted x-2) was deposited on an interfacial layer(IL) of native oxide (SiO, t∼1.2 nm) surface on 200 mm Si wafers by a manufacturable atomic layer chemical vapor deposition technique at 30$0^{\circ}C$. Some as-deposited layers were subjected to a post-deposition, rapid thermal annealing at $700^{\circ}C$ for 5 min in flowing oxygen at atmospheric pressure. The experimental x-ray diffraction, x-ray photoelectron spectroscopy, high-resolution transmission electron microscopy, and high-resolution parallel electron energy loss spectroscopy results showed that a multiphase and heterogeneous structure evolved, which we call the Zr-O/IL/Si stack. The as-deposited Zr-O layer was amorphous $ZrO_2$-rich Zr silicate containing about 15% by volume of embedded $ZrO_2$ nanocrystals, which transformed to a glass nanoceramic (with over 90% by volume of predominantly tetragonal-$ZrO_2$(t-$ZrO_2$) and monoclinic-$ZrO_2$(m-$ZrO_2$) nanocrystals) upon annealing. The formation of disordered amorphous regions within some of the nanocrystals, as well as crystalline regions with defects, probably gave rise to lattice strains and deformations. The interfacial layer (IL) was partitioned into an upper Si $o_2$-rich Zr silicate and the lower $SiO_{x}$. The latter was sub-toichiometric and the average oxidation state increased from Si0.86$^{＋}$ in $SiO_{0.43}$ (as-deposited) to Si1.32$^{＋}$ in $SiO_{0.66}$ (annealed). This high oxygen deficiency in $SiO_{x}$ indicative of the low mobility of oxidizing specie in the Zr-O layer. The stacks were characterized for their dielectric properties in the Pt/{Zr-O/IL}/Si metal oxide-semiconductor capacitor(MOSCAP) configuration. The measured equivalent oxide thickness (EOT) was not consistent with the calculated EOT using a bilayer model of $ZrO_2$ and $SiO_2$, and the capacitance in accumulation (and therefore, EOT and kZr-O) was frequency dispersive, trends well documented in literature. This behavior is qualitatively explained in terms of the multi-layer nanostructure and nanochemistry that evolves.ves.ves.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.53.2-53.2
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• 2010

지금까지 능동 구동 디스플레이의 TFT backplane에 사용하고 있는 채널 물질로는 수소화된 비정질 실리콘(a-Si:H)과 저온 폴리실리콘(low temperature poly-Si)이 대표적이다. 수소화된 비정질 실리콘은 TFT-LCD 제조에 주로 사용되는 물질로 제조 공정이 비교적 간단하고 안정적이며, 생산 비용이 낮고, 소자 간 특성이 균일하여 대면적 디스플레이 제조에 유리하다. 그러나 a-Si:H TFT의 이동도(mobility)가 1 cm2/Vs이하로 낮아 Full HD 이상의 대화면, 고해상도, 고속 동작을 요구하는 UD(ultra definition)급 디스플레이를 개발하는데 있어 한계 상황에 다다르고 있다. 또한 광 누설 전류(photo leakage current)의 발생을 억제하기 위해서 화소의 개구율(aperture ratio)을 감소시켜야하므로 패널의 투과율이 저하되고, 게이트 전극에 지속적으로 바이어스를 인가 시 TFT의 문턱전압(threshold voltage)이 열화되는 문제점을 가지고 있다. 문제점을 극복하기 위한 대안으로 근래 투명 산화물 반도체(transparent oxide semiconductor)가 많은 관심을 얻고 있다. 투명 산화물 반도체는 3 eV 이상의 높은 밴드갭(band-gap)을 가지고 있어 광 흡수도가 낮아 투명하고, 광 누설 전류의 영향이 작아 화소 설계시 유리하다. 최근 다양한 조성의 산화물 반도체들이 TFT 채널 층으로의 적용을 목적으로 활발하게 연구되고 있으며 ZnO, SnO2, In2O3, IGO(indium-gallium oxide), a-ZTO(amorphous zinc-tin-oxide), a-IZO (amorphous indium-zinc oxide), a-IGZO(amorphous indium-galliumzinc oxide) 등이 그 예이다. 이들은 상온 또는 $200^{\circ}C$ 이하의 낮은 온도에서 PLD(pulsed laser deposition)나 스퍼터링(sputtering)과 같은 물리적 기상 증착법(physical vapor deposition)으로 손쉽게 증착이 가능하다. 특히 이중에서도 a-IGZO는 비정질임에도 불구하고 이동도가 $10\;cm2/V{\cdot}s$ 정도로 a-Si:H에 비해 월등히 높은 이동도를 나타낸다. 이와 같이 a-IGZO는 비정질이 가지는 균일한 특성과 양호한 이동도로 인하여 대화면, 고속, 고화질의 평판 디스플레이용 TFT 제작에 적합하고, 뿐만 아니라 공정 온도가 낮은 장점으로 인해 플렉시블 디스플레이(flexible display)의 backplane 소재로서도 연구되고 있다. 본 실험에서는 rf sputtering을 이용하여 증착한 a-IGZO 박막에 대하여 열처리 조건 변화에 따른 a-IGZO 박막들의 광학적, 전기적 특성변화를 살펴보았고, 이와 더불어 a-IGZO 박막을 TFT에 적용하여 소자의 특성을 분석함으로써, 열처리에 따른 Transfer Curve에서의 우리가 요구하는 Threshold Voltage(Vth)의 변화를 관찰하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.169-169
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• 2010

As display industry requires various applications for future display technology, which can guarantees high level of flexibility and transparency on display panel, oxide semiconductor materials are regarded as one of the best candidates. $InGaZnO_4$(IGZO) has gathered much attention as a post-transition metal oxide used in active layer in thin-film transistor. Due to its high mobility fabricated at low temperature fabrication process, which is proper for application to display backplanes and use in flexible and/or transparent electronics. Electrical performance of amorphous oxide semiconductors depends on the resistance of the interface between source/drain metal contact and active layer. It is also affected by sheet resistance on IGZO thin film. Controlling contact/sheet resistance has been a hot issue for improving electrical properties of AOS(Amorphous oxide semiconductor). To overcome this problem, post-annealing has been introduced. In other words, through post-annealing process, saturation mobility, on/off ratio, drain current of the device all increase. In this research, we studied on the relation between device's resistance and post-annealing temperature. So far as many post-annealing effects have been reported, this research especially analyzed the change of electrical properties by increasing post-annealing temperature. We fabricated 6 main samples. After a-IGZO deposition, Samples were post-annealed in 5 different temperatures; as-deposited, $100^{\circ}C$, $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$ and $500^{\circ}C$. Metal deposition was done on these samples by using Mo through E-beam evaporation. For analysis, three analysis methods were used; IV-characteristics by probe station, surface roughness by AFM, metal oxidation by FE-SEM. Experimental results say that contact resistance increased because of the metal oxidation on metal contact and rough surface of a-IGZO layer. we can suggest some of the possible solutions to overcome resistance effect for the improvement of TFT electrical performances.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.273.2-273.2
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• 2014

Sputtering process has been widely used in Si-based semiconductor industry and it is also an ideal method to deposit transparent oxide materials for thin-film transistors (TFTs). The oxide films grown at low temperature by conventional RF sputtering process are typically amorphous state with low density including a large number of defects such as dangling bonds and oxygen vacancies. Those play a crucial role in the electron conduction in transparent electrode, while those are the origin of instability of semiconducting channel in oxide TFTs due to electron trapping. Therefore, post treatments such as high temperature annealing process have been commonly progressed to obtain high reliability and good stability. In this work, the scheme of electron-assisted RF sputtering process for high quality transparent oxide films was suggested. Through the additional electron supply into the plasma during sputtering process, the working pressure could be kept below $5{\times}10-4Torr$. Therefore, both the mean free path and the mobility of sputtered atoms were increased and the well ordered and the highly dense microstructure could be obtained compared to those of conventional sputtering condition. In this work, the physical properties of transparent oxide films such as conducting indium tin oxide and semiconducting indium gallium zinc oxide films grown by electron-assisted sputtering process will be discussed in detail. Those films showed the high conductivity and the high mobility without additional post annealing process. In addition, oxide TFT characteristics based on IGZO channel and ITO electrode will be shown.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.13.1-13.1
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• 2009

Transparent electronics has attracted many interests, for it can open new applications for consumer electronics, transportation, business, and military. Among them, display backplane, thin film transistor (TFT) array would be the most attractive application. Many researchers have been investigating oxide semiconductors for transparent channel material of TFT since the report for transparent amorphous oxide semiconductor (TAOS) TFT by Hosono group and ZnO TFT by Wager group. Especially, oxide TFTs have been intensively investigated during a couple of years since the first demonstration of ZnO-TFT driving AM-OLED. Many papers regarding the fabrication and performance of oxide TFTs, and active matrix display driven by oxide TFTs have been reported. Now lots of people have confidence in the competitiveness of oxide TFTs for the backplane of AM-Display. Especially, high mobility, uniformity, fairly good stability, and low cost process make oxide TFTs applied even to a large size AM-OLED. Last year, Samsung mobile display, former SID, reported 12" AM-OLED driven by IZGO-TFT and it seems that the remained issue for the mass production is the bias temperature stability. Here, we will introduce the application of oxide TFT and important issue for oxide TFT to be used for the direct printing.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.83-89
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• 1989

Ferroelectric $PbTiO_3$ thin film is deposited with rf sputtering at substrate temperature of $100-150^{\circ}C$. It is found that this has pyrochlore structure of amorphous type by X-ray diffractive analysis. Thermal annealing has excellent characteristics at $550^{\circ}C$ and laser annealing has best crystalline structure in case of scanning with 50 watts. Interface states in MFST and MFOST structure with a $PbTiO_3$ ferroelectric thin film gate have been investigated from analysis of C-V data. The interface states density has been drastically reduced by inserting an oxide layer between ferroelectric and semiconductor. The observed effect increase feasibility of employing ferroelectric thin films such as nonvolatile memory field effect transistor, IR optical FET, and Image Devices with a ferroelectric layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Journal of the Korean Ceramic Society
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• v.52 no.4
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• pp.290-293
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• 2015

The properties of the IZTO thin films on the glass were studied with a variation of the $SiO_2$ buffer layer thickness. $SiO_2$ buffer layers were deposited by plasma-enhanced chemical vapor deposition (PECVD) on the glass, and the In-Zn-Tin-Oxide (IZTO) thin films were deposited on the buffer layer by RF magnetron sputtering. All the IZTO thin films with the $SiO_2$ buffer layer are shown to be amorphous. Optimum $SiO_2$ buffer layer thickness was obtained through analyzing the structural, morphological, electrical, and optical properties of the IZTO thin films. As a result, the IZTO surface roughness is 0.273 nm with a sheet resistance of $25.32{\Omega}/sq$ and the average transmittance is 82.51% in the visible region, at a $SiO_2$ buffer layer thickness of 40 nm. The result indicates that the uniformity of surface and the properties of the IZTO thin film on the glass were improved by employing the $SiO_2$ buffer layer and the IZTO thin film can be applied well to the transparent conductive oxide for display devices.

• Transactions on Electrical and Electronic Materials
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• v.15 no.4
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• pp.207-212
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• 2014

Aluminum-doped zinc oxide (AZO) films were deposited on SiOC/Si wafer by an RF-magnetron sputtering system, by varying the deposition parameters of radio frequency power from 50 to 200 W. To assess the correlation of the optical properties between the substrate and AZO thin film, photoluminescence was measured, and the origin of deep level emission of AZO thin films grown on SiOC/Si wafer was studied. AZO formed on SiOC/Si substrates exhibited ultraviolet emission due to exciton recombination, and the visible emission was associated with intrinsic and extrinsic defects. For the AZO thin film deposited on SiOC at low RF-power, the deep level emission near the UV region is attributed to an increase of the variations of defects related to the AZO and SiOC layers. The applied RF-power influenced an energy gap of localized trap state produced from the defects, and the gap increased at low RF power due to the formation of new defects across the AZO layer caused by lattice mismatch of the AZO and SiOC films. The optical properties of AZO films on amorphous SiOC compared with those of AZO film on Si were considerably improved by reducing the roughness of the surface with low surface ionization energy, and by solving the problem of structural mismatch with the AZO film and Si wafer.