• Journal of Elementary Mathematics Education in Korea
• /
• v.18 no.1
• /
• pp.105-122
• /
• 2014

In this paper, fraction division algorithms in Korean elementary mathematics textbooks are analyzed as a part of the groundwork to improve teaching methods for fraction division algorithms. There are seemingly six fraction division algorithms in ${\ll}Math\;5-2{\gg}$, ${\ll}Math\;6-1{\gg}$ textbooks according to the 2006 curriculum. Four of them are standard algorithms which show the multiplication by the reciprocal of the divisors modally. Two non-standard algorithms are independent algorithms, and they have weakness in that the integration to the algorithms 8 is not easy. There is a need to reconsider the introduction of the algorithm 4 in that it is difficult to think algorithm 4 is more efficient than algorithm 3. Because (natural number)${\div}$(natural number)=(natural number)${\times}$(the reciprocal of a natural number) is dealt with in algorithm 2, it can be considered to change algorithm 7 to algorithm 2 alike. In textbooks, by converting fraction division expressions into fraction multiplication expressions through indirect methods, the principles of calculation which guarantee the algorithms are explained. Method of using the transitivity, method of using the models such as number bars or rectangles, method of using the equivalence are those. Direct conversion from fraction division expression to fraction multiplication expression by handling the expression is possible, too, but this is beyond the scope of the curriculum. In textbook, when dealing with (natural number)${\div}$(proper fraction) and converting natural numbers to improper fractions, converting natural numbers to proper fractions is used, but it has been never treated officially.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.59-67
• /
• 2009

In this paper, we have proposed the structure of the IMADF(improved modified multiplication-free adaptive filter) to cancel the adaptive noise in biomedical signals. The IMADF structure use the one-step predicted filter in the multiplication-free adaptive digital filter(MADF) structure using the DPCM and Sign algorithm. And then we use the heart phantom model based on the magnetocardiographic (MCG) to test the biomedical signals and analyze the signal of it. Their functions of the heart phantom occur from the multidipole current source. This can play role the same in the real function of the human heart to study it. In the experimental results, the IMADF algorithm has reduced the computational complexity by use of only the addition operation without a multiplier. Also, under the condition of identical stationary-state error, it could obtain the stabled convergence characteristics that the IMADF algorithm is almost same as the sign algorithm, but is better than the MADF algorithm. Here, this algorithm has effective characteristics when the correlation of the input signal is highly.

• 제어로봇시스템학회:학술대회논문집
• /
• 1997.10a
• /
• pp.1379-1382
• /
• 1997

We introduce a fast implementation of the adaptive transversal filter which uses least-mean-square(LMS) algorithm. The fast Hadamard transform(FHT) is used for the implementation of the filter. By using the proposed filter we can get the significant time reduction in computatioin over the conventional time domain LMS filter at the cost of a little performance. By computer simulation, we show the comparison of the propsed Hadamard-domain filter and the time domain filter in the view of multiplication time, mean-square error and robustness for noise.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.9A
• /
• pp.1346-1353
• /
• 1999

We propose the MADF(multiplication free adaptive digital filter) algorithm and implement the fractionally spaced equalizer based on it. To evaluate the performance of proposed MADF algorithm, fractionally spaced equalizer(FSE) is used. Especially, we present that this method have the advantages for the condition having the low-frequency and slow speed

• Journal of information and communication convergence engineering
• /
• v.8 no.1
• /
• pp.23-28
• /
• 2010

According to increasing projection order, the AP algorithm bas noise amplification problem in large background noise. This phenomenon degrades the performances of the AP algorithm. In this paper, we analyze convergence characteristic of the AP algorithm and then suggest a noise robust modified AP algorithm for reducing this problem. The proposed algorithm normalizes the update equation to reduce noise amplification of AP algorithm, by adding the multiplication of error power and projection order to auto-covariance matrix of input signal. By computer simulation, we show the improved performance than conventional AP algorithm.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.895-900
• /
• 2020

In this paper, BSPE replaced the existing multiplication algorithm that consumes a lot of power. Hardware resources are reduced by using a bit-serial multiplier, and variable integer data is used to reduce memory usage. In addition, MOA resource usage and power usage were reduced by applying LOA (Lower-part OR Approximation) to MOA (Multi Operand Adder) used to add partial sums. Therefore, compared to the existing MBS (Multiplication by Barrel Shifter), hardware resource reduction of 44% and power consumption of 42% were reduced. Also, we propose a hardware architecture design for BSPE Core.

• Journal of the Korea Society of Computer and Information
• /
• v.25 no.2
• /
• pp.41-48
• /
• 2020

In this paper, we derive a common computational part in an algorithm that can simultaneously perform multiplication and square over finite fields, and propose a low-area bit-parallel systolic array that reduces hardware through sequential processing. The proposed systolic array has less space and area-time (AT) complexity than the existing related arrays. In detail, the proposed systolic array saves about 48% and 44% of Choi-Lee and Kim-Kim's systolic arrays in terms of area complexity, and about 74% and 44% in AT complexity. Therefore, the proposed systolic array is suitable for VLSI implementation and can be applied as a basic component in hardware constrained environment such as IoT.

• Proceedings of the Korean Information Science Society Conference
• /
• 2000.10a
• /
• pp.590-592
• /
• 2000

Operator-level optimization of a systolic array for Montgomery Modular Multiplication(MMM) algorithm is presented in thin paper. The proposed systolic array is faster than that of C.D. Walter by 40%. Compared with J.B. Shin et al.'s, it is 25% faster.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.10
• /
• pp.69-76
• /
• 1993

In this paper we propose a design of a digital neuron processor using the residue number system for efficient matrix.vector multiplication involved in neural processing. Since the residue number system needs no carry propagation for modulus operations, the neuron processor can perform multiplication considerably fast. We also propose a high speed algorithm for computing the sigmoid function using the specially designed look-up table. Our method can be implemented area-effectively using the current technology of digital VLSI and siumlation results positively demonstrate the feasibility of our method. The proposed method would expected to adopt for application field of digital neural network, because it could be realized to currently developed digital VLSI Technology.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.11 no.3
• /
• pp.270-276
• /
• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.