• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.59-67
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• 2016

With the enhancement of built-in communication capabilities in various meters and wearable devices, which implies Internet of things (IoT), the demand of small-area embedded processors has increased. In this paper, we introduce a small-area 32-bit pipelined processor, Juno, which is available in the field of IoT. Juno is an EISC (Extendable Instruction Set Computer) machine and has a 2/3-stage pipeline structure to reduce the data dependency of the pipeline. It has a simple pipeline controller which only controls the program counter (PC) and two pipeline registers. It offers $32{\times}32=64$ multiplication, 64/32=32 division, $32{\times}32+64=64$ MAC (multiply and accumulate) operations together with 32*32=64 Galois field multiplication operation for encryption processing in wireless communications. It provides selective inclusion of these algebraic logic blocks if necessary in order to reduce the area of the overall processor. In this case, the gate count of our integer core amounts to 12k~22k and has a performance of 0.57 DMIPS/MHz and 1.024 Coremark/MHz.

• Journal for History of Mathematics
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• v.21 no.4
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• pp.1-10
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• 2008

In this paper, we investigate the part dealing with algebra in Hong Gil Ju's GiHaSinSul to analyze his algebraic structure. The book consists of three parts. In the first part SangChuEokSan, he just renames Die jie hu zheng(疊借互徵) in Shu li jing yun to SangChuEokSan and adds a few examples. In the second part GaeBangMongGu, he obtains the following identities: $$n^2=n(n-1)+n=2S_{n-1}^1+S_n^0;\;n^3=n(n-1)(n+1)+n=6S_{n-1}^2+S_n^0$$; $$n^4=(n-1)n^2(n+1)+n(n-1)+n=12T_{n-1}^2+2S_{n-1}^1+S_n^0$$; $$n^5=2\sum_{k=1}^{n-1}5S_k^1(1+S_k^1)+S_n^0$$ where $S_n^0=n,\;S_n^{m+1}={\sum}_{k=1}^nS_k^m,\;T_n^1={\sum}_{k=1}^nk^2,\;and\;T_n^2={\sum}_{k=1}^nT_k^1$, and then applies these identities to find the nth roots $(2{\leq}n{\leq}5)$. Finally in JabSwoeSuCho, he introduces the quotient ring Z/(9) of the ring Z of integers to solve a system of congruence equations and also establishes a geometric procedure to obtain golden sections from a given one.

• Spatial Information Research
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• v.9 no.2
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• pp.239-261
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• 2001

A large suite of official statistical data sets has been compiled for geographical units under the national directives, and it is the quantitative regional analysis procedures that could add values to them. This paper reports our attempts at prototyping a statistical GIS which is capable of serving over the Web a variety of regional analysis routines as well as value-added statistics and maps. A pilot database of some major statistical data was ingested for the city of Seoul. The baseline subset of regional analysis methods of practical usage was selected and accommodated into the business logic of the target system, which ranges from descriptive statistics, regional structure/inequality measures, spatial ANOVA, spatial (auto) correlation to regression and residual analysis. The leading-edge information technologies including the application server were adopted in the system design and implementation so that the database, analysis modules and analytic mapping components may cooperate seamlessly behind the Web front-end. The prototyped system supports tables, maps, and files of downloadable format for input and output of the analyses. One of the most salient features of out proposed system is that both the database and analysis modules are extensible via the bi-directional interface for end users; The system provides users with operators and parsers for algebraic formulae such that the stored statistical variables may be transformed and combined into the newly-derived set of variables. This functionality eventually leads to on-the-fly fabrication of user-defined regional analysis algorithms. The stored dataset may also be temporarily augmented by user-uploaded dataset; The extension of this form, in essence, results in a virtual database which awaits for users commands as usual. An initial evaluation of the proposed system confirms that the issues involving the usage and dissemination of information can be addressed with success.