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http://dx.doi.org/10.5573/ieie.2016.53.4.059

Low-Gate-Count 32-Bit 2/3-Stage Pipelined Processor Design  

Lee, Kwang-Min (Dept. Electronics Eng., Pusan National University)
Park, Sungkyung (Dept. Electronics Eng., Pusan National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.53, no.4, 2016 , pp. 59-67 More about this Journal
Abstract
With the enhancement of built-in communication capabilities in various meters and wearable devices, which implies Internet of things (IoT), the demand of small-area embedded processors has increased. In this paper, we introduce a small-area 32-bit pipelined processor, Juno, which is available in the field of IoT. Juno is an EISC (Extendable Instruction Set Computer) machine and has a 2/3-stage pipeline structure to reduce the data dependency of the pipeline. It has a simple pipeline controller which only controls the program counter (PC) and two pipeline registers. It offers $32{\times}32=64$ multiplication, 64/32=32 division, $32{\times}32+64=64$ MAC (multiply and accumulate) operations together with 32*32=64 Galois field multiplication operation for encryption processing in wireless communications. It provides selective inclusion of these algebraic logic blocks if necessary in order to reduce the area of the overall processor. In this case, the gate count of our integer core amounts to 12k~22k and has a performance of 0.57 DMIPS/MHz and 1.024 Coremark/MHz.
Keywords
small area; low gate count; embedded processor; IoT (Internet of things);
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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