• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.295-298
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• 2014

In this paper, an efficient design of HEVC Adaptive Loop Filter(ALF) for filter coefficients estimation is proposed. The ALF performs Cholesky decomposition of $10{\times}10$ matrix iteratively to estimate filter coefficients. The Cholesky decomposition of the ALF consists of root and division operation which is difficult to implement in a hardware design because it needs to many computation rate and processing time due to floating-point unit operation of large values of the Maximum 30bit in a LCU($64{\times}64$). The proposed hardware architecture is implemented by designing a root operation based on Cholesky decomposition by using multiplexer, subtracter and comparator. In addition, The proposed hardware architecture of efficient and low computation rate is implemented by designing a pipeline architecture using characteristic operation steps of Cholesky decomposition. An implemented hardware is designed using Xilinx ISE 14.3 Vertex-6 XC6VCX240T FPGA device and can support a frame rate of 40 4K Ultra HD($4096{\times}2160$) frames per second at maximum operation frequency 150MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.405-410
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• 2012

This paper presents an inductorless 8-Gb/s adaptive passive equalizer with low-power consumption and small chip area. The equalizer has a tunable RC filter which provides high-frequency gain boosting and a limiting amplifier that restores the signal level from the filter output. It also includes a feedback loop which automatically adjusts the filter gain for the optimal frequency response. The equalizer fabricated in $0.18-{\mu}m$ CMOS technology can successfully equalize 8-Gb/s data transmitted through up to 50-cm FR4 PCB channels. It consumes 6.75 mW from 1.8-V supply voltage and occupies $0.021mm^2$ of chip area.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8C
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• pp.583-590
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• 2008

In this paper, we present a spatially adaptive post-processing algorithm for H.264 video coding standard to remove blocking artifacts. The loop filter of H.264 increases computational complexity of the encoder. Furthermore it doesn't clearly remove the blocking artifacts, resulting in over-blurring. For overcoming them, we combine the projection method with the Constraint Least Squares(CLS) method to restore the high quality image. To reflect the Human Visual System, we adopt the weight norm CLS method. Particularly pixel location-based local variance and laplacian operator are newly defined for the CLS method. In addition, the fact that correlation among adjoining pixels is high is utilized to constrain the solution space when the projection method is applied. Quantization Index(QP) of H.264 is also used to control the degree of smoothness. The simulation results show that the proposed post-processing filter works better than the loop filter of H.264 and converges more quickly than the CLS method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• Journal of Power Electronics
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• v.12 no.5
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• pp.800-812
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• 2012

This paper analyses the mathematical model and control strategies of a Hybrid Active Power Filter with Injection Circuit (IHAPF). The control strategy based on the load harmonic current detection is selected. A novel control method for a IHAPF, which is based on the analyzed control mathematical model, is proposed. It consists of two closed-control loops. The upper closed-control loop consists of a single fuzzy logic controller and the IHAPF model, while the lower closed-control loop is composed of an Adaptive Network based Fuzzy Inference System (ANFIS) controller, a Neural Generalized Predictive (NGP) regulator and the IHAPF model. The purpose of the lower closed-control loop is to improve the performance of the upper closed-control loop. When compared to other control methods, the simulation and experimental results show that the proposed control method has the advantages of a shorter response time, good online control and very effective harmonics reduction.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1047-1053
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• 2011

In this paper, we proposed an HF-band wireless power transfer system with adaptive frequency control circuit for efficiency enhancement in a short range. In general, a wireless power transfer system shows an impedance mismatching due to a reflected impedance, because a coupling coefficient is varied with respect to separation distance between two resonating loop antennas. The proposed method can compensate this impedance mismatching by varying input frequency of a voltage-controlled oscillator adaptively with respect to separation distance. Therefore, transmission efficiency is enhanced in a short distance, where large impedance mismatch occurs. The adaptive frequency circuit consists of a directional coupler, a detector, and a loop filter. In order to demonstrate the performance of the proposed system, a wireless power transfer system with adaptive frequency control circuits is designed and implemented, which has a pair of loop antennas with a dimension of 30${\times}$30 $cm^2$. From measured results, the proposed system shows enhanced efficiency performance than the case without adaptive frequency control.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.113-120
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• 2014

In this paper, I present a new echo canceller using the adaptive cascade system identification (CSI) method, which a system response is divided into several responses so that each response is adaptively estimated and combined. Echo cancellation is required for a dual-duplex DSL, in order to allow each individual loop to operate in a full duplex fashion. Echo cancellation was one of the most difficult aspects of DSL design, requiring high linearity and total echo return loss in excess of 70 dB. Especially, for a fickle response, if the response is estimated by an adaptive filter, the filter needs more taps and the performance is decreased. But the response is divided into several responses, the computation complexities are decreased and the performance is increased. For the stage constant n, which represents the number of stages, if the response is not divided (n=1), the computation complexity of multiply is $2N^2$. And if the response is divided into two responses (n=2), the computation complexity of multiply is $2N^2$. Also, if n=3, the computation complexity is ${\frac{2}{3}}N^2$. Therefore, it is known that the computation complexity is decreased as n is increased. Finally, this proposed method is verified through simulation of echo canceller for digital subscriber line (DSL) application.

• Journal of Power Electronics
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• v.14 no.4
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• pp.742-753
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• 2014

In this paper, a new continuously and linearly controlled capacitive static VAR compensator is proposed for the automatic power factor correction of inductive single phase loads in 220V 50Hz power system networks. The compensator is constructed of a harmonic-suppressed TCR equipped with a new adaptive current controller. The harmonic-suppressed TCR is a new configuration that includes a thyristor controlled reactor (TCR) shunted by a passive third harmonic filter. In addition, the parallel configuration is connected to an AC source via a series first harmonic filter. The harmonic-suppressed TCR is designed so that negligible harmonic current components are injected into the AC source. The compensator is equipped with a new adaptive closed loop current controller, which responds linearly to reactive current demands. The no load operating losses of this compensator are negligible when compared to its capacitive reactive current rating. The proposed system is validated on PSpice which is very close in terms of performance to real hardware.

• The Journal of the Acoustical Society of Korea
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• v.14 no.3
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• pp.28-36
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• 1995

In this paper, a double loop control model using leaky delay LMS algorithm are proposed for active noise control. The proposed double loop control model estimates the loudspeaker characteristic and the error path transfer function with on-line using only gain and acoustic time delay to reduce computation burden. The control of error signal through double loop control scheme makes the more robust cntrol system. The input signal of filter to estimate acoustic time delay is used difference between input signal of input microphone and adaptive filter output. And also, in nonstationary environments, the leaky delay LMS algorithm is employed to counteract parameter drift of delay LMS algorithm. For practical noise signal, the proposed double loop control model reduces noise level about 12.9 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.10 s.340
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• pp.1-8
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• 2005

This Paper Proposes the algorithm for improving the Performance or symbol timing synchronization in hoc terrestrial DTV system. The Gardner algerian is used for symbol timing synchronization has good performance in multipath fading environment but degradation of performance is caused by jitter. Though the amount of jitter becomes more little as narrow bandwidth of loop Inter, convergence speed becomes slower. This paper propose the algorithm that averages out values of loop filter every certain time and gradually reduces the bandwidth of loop filter after estimating offset using this average for the high speed of convergence and reducing the met of jitter. The proposed algorithm has better performance with high speed of convergence and the amount of jitter than conventional method.