• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.356-356
• /
• 2010

In this paper, Poly silicon thin-film transistors (poly-Si TFTs) with employed the SPC (Solid phase crystallization) and ELA (Excimer laser annealing) methods on glass panel substrate are fabricated to investigate the electrical poperies. Poly-Si TFTs have recess-channel structure with formated source/drain regions by LPCVD n+ poly Si in low $650^{\circ}C$ temperature. the ELA-TFT show higher on/off current ratio and subthreshold swing than a-Si and SPC TFT that therefore, these results showed that the ELA-TFT might be beneficial for practical embedded TFT memory device application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.320-323
• /
• 2000

In the resent years, the Thin Film Transistor Liquid Crystal Display(TFT-LCD) have trend toward larger panel sizes and higher spatial and/or gray-scale resolution. In this trend, Because of its low field effect mobility, a-Si TFT is change to poly-Si TFT. In this paper, both effective-medium model of poly-Si TFTs and empirical capacitance model are applied to Pixel Design Array Simulation Tool (PDAST) and the pixel characteristics of TFT-LCD array were simulated, which were compared with the results calculated by Aim-Spice.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1238_1239
• /
• 2009

본 논문에서는 ELA poly-Si TFT보다 뛰어난 균일도를 갖고, a-Si:H TFT보다 전기적 안정도가 우수한 PMOS SPC-Si TFT의 특성을 연구하였다. SPC-Si의 계면 특성을 향상 시키기 위해 $SiO_2$ 게이트 절연막을 증착하기 전에 Solid Phase Crystalline 실리콘(SPC-Si) 채널 영역에 다양한 H2 플라즈마 처리를 해주었다. PECVD를 이용하여 100W에서 H2 플라즈마 처리를 5분 해주었을 때 SPC-Si TFT의 전기적 특성이 향상되는 것을 볼 수 있는데, $V_{TH}$가 약 -3.91V, field effect mobility가 $22.68cm^2$/Vs, 그리고 Subthreshold swing이 0.64 정도를 보였다. 또한 소자에 Hot carrier stress($V_{GS}$=14.91V, $V_{DS}$=-15V, for 2,000sec)를 주었을 때도 전기적 특성이 변하지 않았으며, 일정한 bias stress($V_{GS}$=-15V, $V_{DS}$=-10V, for 2,000sec)를 가하였을 때도 $V_{TH}$가 증가하지 않았다. 이러한 결과를 통해 SPC-Si가 poly-Si TFT보다 더욱 안정함을 알 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.6
• /
• pp.1099-1103
• /
• 2007

TFT's have been intensively researched for possible electronic and display applications. Through tremendous engineering and scientific efforts, a-Si:H TFT fabrication process was greatly improved. In this paper, the reason on defects occurring at a-Si:H TFT fabrication process is analyzed and solved, so a-Si:H TFT's yield is increased and reliability is improved. The a-Si:H TFT of this paper is inverted staggered type TFT. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr). We have fabricated a-SiN:H, conductor, etch-stopper and photo-resistor on gate electrode in sequence, respectively. We have deposited n+a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-slower pattern. The NPR layer by inverting pattern of upper Sate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFT made like this has problems at photo-lithography process caused by remains of PR. When sample is cleaned, this remains of PR makes thin chemical film on surface and damages device. Therefor, in order to improve this problem we added ashing process and cleaning process was enforced strictly. We can estimate that this method stabilizes fabrication process and makes to increase a-Si:H TFT's yield.

• Journal of the Korean Vacuum Society
• /
• v.10 no.1
• /
• pp.72-80
• /
• 2001

In this paper, we present a systematic method of extracting the input parameters of poly-Si TFT(Thin-Film Transistor) for Spice simulations. This method has been applied to two different types of poly-Si TFTs such as ELA (Excimer Laser Annealing) and SMC (Silicide Mediated Crystallization) with good fitting results to experimental data. Among the Spice circuit simulators, the PSpice has the GUI(graphic user interface) feature making the composition of complicated circuits easier. We added successfully the poly-Si TFT model of AIM-Spice to the PSpice simulator, and analyzed easily to compare the electrical characteristics of pixels without or with the line RC delay. In the comparative results, the ELA poly-Si TFT is superior to the SMC poly-Si TFT in the charging time and the kickback voltage for the TFT-LCD (Thin Film Transistor-Liquid Crystal Display).

• 한국정보디스플레이학회:학술대회논문집
• /
• 2004.08a
• /
• pp.395-398
• /
• 2004

We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA(240$^{\ast}$320) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.04a
• /
• pp.169-172
• /
• 2000

A-Si:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly-Si films were achieved by various anneal techniques ; isothermal, RTA, and excimer laser anneal. The TFT on as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from $200^{\circ}C$ to $1000^{\circ}C$. The TFT on poly-Si showed an improved $I_{on}/I_{off}$ ratio of $10^6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly-Si TFTs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.9
• /
• pp.683-686
• /
• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2000.01a
• /
• pp.67-68
• /
• 2000

Polycrystalline silicon (poly-Si) thin film transistors (TFT's) employing vertical amorphous silicon (a-Si) offsets have been fabricated without additional photolithography processes. The a-Si offset has been formed utilizing the poly-Si grain growth blocking effect by thin native oxide film during the excimer laser recrystallization of a-Si. The ON current degradation of the new device after 4 hour's electrical stress was reduced by 5 times compared with conventional poly-Si TFT's.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.12
• /
• pp.122-129
• /
• 1995

The most important feature of a-Si TFT is dense localized states such as dangling bonds which exist in tis bandgap. Electrons trapped by localized states dominate the potential distribution in the active a-Si region ,and influence the performance of a-Si TFT. In this paper, we describe the electrical characteristics of a-Si TFT with respect to trap distribution within bandgap, electron mobility and interface states using 2-Dimensional device simulator and compare the result of simulation with measurements. Using the mixed-mode simulator, we can predict the potential variation of pixel which causes residual image problem during the turn-off of a-Si TFT driving circuit. Therefore it is possible to consider trade-off between potential variation of pixel and turn-on current of a-Si TFT for the optimized driving circuit.