• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.91-91
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• 2000

a-C:H 혹은 a-SiC:H 박막은 광전소자 및 태양전지 등의 개발에 있어서 중요한 물질이다. 우리는 a-C:H 및 a-SiC:H 박막을 PECVD (plasma-enhanced chemical vapor deposition) 방법으로 증착시키고, 박막의 가열에 따른 스핀밀도의 변화를 ESR (electron spin resonance) 측정을 통하여 조사하였다. PECVD 증착가스는 Ch4, SiH4 가스를 사용하였고, 기판은 Corning 1737glass를 사용하였으며, 기판 온도는 300-40$0^{\circ}C$, 증착 압력은 0.1-0.3 Torr, r.f. 전력은 3-36W 사이에서 변화되었다. ESR 측정은 상온 X-band 영역에서 수행되었고, modulation amplitude는 2.5G, modulation frequency는 100kHz 이었다. a-C:H 혹은 a-SiC:H 박막은 진공상태의 reactor, 혹은 공기중의 furnace 안에서 300-50$0^{\circ}C$ 영역에서 3-8시간 정도 가열되거나, 혹은 상온에서 약 50$0^{\circ}C$ 정도까지 단계적으로 가열되었다. 증착된 a-C:H 박막의 초기 구조는 Raman 측정으로부터 polymer-like Carbon으로 추정되었으며, 300-35$0^{\circ}C$ 가열시 초기 1시간 정도 사이에는 스핀밀도가 증가되었으나, 그 후 8시간 정도까지의 가열의 경우에도 대체로 동일하게 나타났다. 또한 상온으로부터 약 50$0^{\circ}C$까지 단계적으로 온도를 높여주며, 각 단계마다 1시간씩 가열했을 때도 30$0^{\circ}C$ 정도까지는 스핀밀도가 증가하다가 더 높은 온도로 가면서 다시 스핀밀도가 감소함을 볼 수 있었다. 이러한 스핀밀도의 초기 증가 및 감소를 일으키는 메카니즘에 대해서 논의해 볼 것이다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.181-181
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• 2016

Hydrogenated microcrystalline silicon (${\mu}c-Si:H$) films have attracted much attention as materials of the bottom-cells in Si thin film tandem photovoltaics due to their low bandgap and excellent stability against light soaking. However, in PECVD, the source gas $SiH_4$ must be highly diluted by $H_2$, which eventually results in low deposition rate. Moreover, it is known that high-rate ${\mu}c-Si:H$ growth is usually accompanied by a large number of dangling-bond (DB) defects in the resulting films, which act as recombination centers for photoexcited carriers, leading to a deterioration in the device performance. During film deposition, Si nanoparticles generated in $SiH_4$ discharges can be incorporated into films, and such incorporation may have effects on film properties depending on the size, structure, and volume fraction of nanoparticles incorporated into films. Here we report experimental results on the effects of nonoparticles incorporation at the different substrate temperature studied using a multi-hollow discharge plasma CVD method in which such incorporation can be significantly suppressed in upstream region by setting the gas flow velocity high enough to drive nanoparticles toward the downstream region. All experiments were performed with the multi-hollow discharge plasma CVD reactor at RT, 100, and $250^{\circ}C$, respectively. The gas flow rate ratio of $SiH_4$ to $H_2$ was 0.997. The total gas pressure P was kept at 2 Torr. The discharge frequency and power were 60 MHz, 180 W, respectively. Crystallinity Xc of resulting films was evaluated using Raman spectra. The defect densities of the films were measured with electron spin resonance (ESR). The defect density of fims deposited in the downstream region (with nonoparticles) is higher defect density than that in the upstream region (without nanoparticles) at low substrate temperature of RT and $100^{\circ}C$. This result indicates that nanoparticle incorporation can change considerably their film properties depending on the substrate temperature.

• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.112-114
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• 2001

In this letter, we report on the investigation of Si/Ti, Pt/Si/Ti, Co/Si/Ti Ohmic contacts to p-type 4H-SiC. The contacts were formed by a 2-step vacuum annealing at $550^{\circ}C$ for 5 min, $850^{\circ}C$ for 2 min respectively. The contact resistances were measured using the transmission line model method, which resulted in specific $10^{-4}{\Omega}cm^2$, and the physical properties of the contactcontact resistivities in the $9.2{\times}10^{-4}$, $7.1{\times}10^{-4}$ and $4.5{\times}s$ were examined using microscopy, AES(auger electron spectroscopy). AES analysis has shown that, at this anneal temperature, there was a intermixing of the Ti and Si, migration of into SiC. Overlayer of Pt, Co had the effect of decreasing the specific contact resistivity and improving the surface morphology of the annealed contact.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.254-255
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• 2012

Interest in nano-crystalline silicon (nc-Si) thin films has been growing because of their favorable processing conditions for certain electronic devices. In particular, there has been an increase in the use of nc-Si thin films in photovoltaics for large solar cell panels and in thin film transistors for large flat panel displays. One of the most important material properties for these device applications is the macroscopic charge-carrier mobility. Hydrogenated amorphous silicon (a-Si:H) or nc-Si is a basic material in thin film transistors (TFTs). However, a-Si:H based devices have low carrier mobility and bias instability due to their metastable properties. The large number of trap sites and incomplete hydrogen passivation of a-Si:H film produce limited carrier transport. The basic electrical properties, including the carrier mobility and stability, of nc-Si TFTs might be superior to those of a-Si:H thin film. However, typical nc-Si thin films tend to have mobilities similar to a-Si films, although changes in the processing conditions can enhance the mobility. In polycrystalline silicon (poly-Si) thin films, the performance of the devices is strongly influenced by the boundaries between neighboring crystalline grains. These grain boundaries limit the conductance of macroscopic regions comprised of multiple grains. In much of the work on poly-Si thin films, it was shown that the performance of TFTs was largely determined by the number and location of the grain boundaries within the channel. Hence, efforts were made to reduce the total number of grain boundaries by increasing the average grain size. However, even a small number of grain boundaries can significantly reduce the macroscopic charge carrier mobility. The nano-crystalline or polymorphous-Si development for TFT and solar cells have been employed to compensate for disadvantage inherent to a-Si and micro-crystalline silicon (${\mu}$-Si). Recently, a novel process for deposition of nano-crystralline silicon (nc-Si) thin films at room temperature was developed using neutral beam assisted chemical vapor deposition (NBaCVD) with a neutral particle beam (NPB) source, which controls the energy of incident neutral particles in the range of 1~300 eV in order to enhance the atomic activation and crystalline of thin films at room temperature. In previous our experiments, we verified favorable properties of nc-Si thin films for certain electronic devices. During the formation of the nc-Si thin films by the NBaCVD with various process conditions, NPB energy directly controlled by the reflector bias and effectively increased crystal fraction (~80%) by uniformly distributed nc grains with 3~10 nm size. The more resent work on nc-Si thin film transistors (TFT) was done. We identified the performance of nc-Si TFT active channeal layers. The dependence of the performance of nc-Si TFT on the primary process parameters is explored. Raman, FT-IR and transmission electron microscope (TEM) were used to study the microstructures and the crystalline volume fraction of nc-Si films. The electric properties were investigated on Cr/SiO2/nc-Si metal-oxide-semiconductor (MOS) capacitors.

• Journal of IKEEE
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• v.17 no.4
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• pp.428-433
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• 2013

In this study, an 4H-SiC Trench MOS Barrier Schottky (TMBS) rectifier which utilizes the trapezoid mesa structure and the upper half of the trench sidewall is proposed to improve the forward voltage drop and reverse blocking voltage concurrently. The proposed 4H-SiC TMBS rectifier reduces the forward voltage drop by 12% compared to the conventional 4H-SiC TMBS rectifier with the tilted sidewall and improves the reverse blocking voltage by 11% with adjusting the length of the upper sidewall. The Silvaco T-CAD was used to analyze the electrical characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.320-320
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• 2014

Amorphous silicon alloy (a-Si) solar cells and modules have been receiving a great deal of attention as a low-cost alternate energy source for large-scale terrestrial applications. Key to the achievement of high-efficiency solar cells using the multi-junction approach is the development of high quality, low band-gap materials which can capture the low-energy photons of the solar spectrum. Several cell designs have been reported in the past where grading or buffer layers have been incorporated at the junction interface to reduce carrier recombination near the junction. We have investigated profiling the composition of the a-SiGe alloy throughout the bulk of the intrinsic material so as to have a built-in electrical field in a substantial portion of the intrinsic material. As a result, the band gap mismatch between a-Si:H and $a-Si_{1-x}Ge_x:H$ creates a barrier for carrier transport. Previous reports have proposed a graded band gap structure in the absorber layer not only effectively increases the short wavelength absorption near the p/i interface, but also enhances the hole transport near the i-n interface. Here, we modulated the GeH4 flow rate to control the band gap to be graded from 1.75 eV (a-Si:H) to 1.55 eV ($a-Si_{1-x}Ge_x:H$). The band structure in the absorber layer thus became like a U-shape in which the lowest band gap was located in the middle of the i-layer. Incorporation of this structure in the middle and top cell of the triple-cell configuration is expected to increase the conversion efficiency further.

• Journal of the Korean Applied Science and Technology
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• v.16 no.1
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• pp.33-40
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• 1999

We used Cu as a representative of metals to be directly adsorbed on the bare Si surface and studied its removal DHF, DHF-$H_2O_2$ and BHF solution. It has been found that Cu ion in DHF adheres on every Si wafer surface that we used in our study (n, p, n+, p+) especially on the n+-Si surface. The DHF-$H_2O_2$ solution is found to be effective in removing metals featuring high electronegativity such as Cu from the p-Si and n-Si wafers. Even when the DHF-$H_2O_2$ solution has Cu ions at the concentration of 1ppm, the solution is found effective in cleaning the wafer. In the case the n+-Si and p+-Si wafers, however, their surfaces get contaminated with Cu When Cu ion of 10ppb remains in the DHF-$H_2O_2$ solution. When BHF is used, Cu in BHF is more likely to contaminate the n+-Si wafer. It is also revealed that the surfactant added to BHF improve wettability onto p-Si, n-Si and p+-Si wafer surface. This effect of the surfactant, however, is not observed on the n+-Si wafer and is increased when it is immersed in the DHF-$H_2O_2$ solution for 10min. The rate of the metallic contamination on the n+-Si wafer is found to be much higher than on the other Si wafers. In order to suppress the metallic contamination on every type of Si surface below 1010atoms/cm2, the metallic concentration in ultra pure water and high-purity DHF which is employed at the final stage of the cleaning process must be lowered below the part per trillion level. The DHF-$H_2O_2$ solution, however, degrades surface roughness on the substrate with the n+ and p+ surfaces. In order to remove metallic impurities on these surfaces, there is no choice at present but to use the $NH_4OH-H_2O_2-H_2O$ and $HCl-H_2O_2-H_2O$ cleaning.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.573-578
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• 2003

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f$\_$max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH$_2$Cl$_2$ was used as the source of Si SEG(Selective Epitaxial Growth) and GeH$_4$ was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725$^{\circ}C$. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.459-462
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• 2000

A new method for the fabrication of poly-Si films is reported using by alternating magnetic flux crystallization (AMFC) of LPCVD a-Si films. In this work we have studied the crystallization of LPCVD a-Si films by alternating magnetic flux. A-Si films were 1200$\AA$-thick deposited at 48$0^{\circ}C$ at a total pressure of 0.25Torr using Si$_2$H$_{6}$/H$_2$. After this step, these a-Si films were thermally annealed by Alternating Magnetic Flux at 43$0^{\circ}C$ for 1hours. The annealed films were characterized using X-ray diffraction (XRD), Raman Spectra, Atomic Force Microscopy(AFM). Both alternating magnetic flux crystallization and solid phase crystallization were investigated to compare enhanced crystallization a-Si. We have found that the low temperature crystallization method at 43$0^{\circ}C$ by alternating magnetic flux.x.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.3
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• pp.139-143
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• 2017

N-type crystalline silicon solar cells have high metal impurity tolerance and higher minority carrier lifetime that increases conversion efficiency. However, junction quality between the boron diffused layer and the n-type substrate is more important for increased efficiency. In this paper, the current status and prospects for boron diffused layers in N-type crystalline silicon solar cell applications are described. Boron diffused layer formation methods (thermal diffusion and co-diffusion using $a-SiO_X:B$), boron rich layer (BRL) and boron silicate glass (BSG) reactions, and analysis of the effects to improve junction characteristics are discussed. In-situ oxidation is performed to remove the boron rich layer. The oxidation process after diffusion shows a lower B-O peak than before the Oxidation process was changed into $SiO_2$ phase by FTIR and BRL. The $a-SiO_X:B$ layer is deposited by PECVD using $SiH_4$, $B_2H_6$, $H_2$, $CO_2$ gases in N-type wafer and annealed by thermal tube furnace for performing the P+ layer. MCLT (minority carrier lifetime) is improved by increasing $SiH_4$ and $B_2H_6$. When $a-SiO_X:B$ is removed, the Si-O peak decreases and the B-H peak declines a little, but MCLT is improved by hydrogen passivated inactive boron atoms. In this paper, we focused on the boron emitter for N-type crystalline solar cells.