• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.106-106
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• 2011

Recently, zinc oxide (ZnO) thin films have attracted great attention as a promising candidate for various electronic applications such as transparent electrodes, thin film transistors, and optoelectronic devices. ZnO thin films have a wide band gap energy of 3.37 eV and transparency in visible region. Moreover, ZnO thin films can be deposited in a poly-crystalline form even at room temperature, extending the choice of substrates including even plastics. Therefore, it is possible to realize thin film transistors by using ZnO thin films as the active channel layer. In this work, we investigated influence of oxygen partial pressure on ZnO thin films and fabricated ZnO-based thin film transistors. ZnO thin films were deposited on glass substrates by using a pulsed laser deposition technique in various oxygen partial pressures from 20 to 100 mTorr at room temperature. X-ray diffraction (XRD), transmission line method (TLM), and UV-Vis spectroscopy were employed to study the structural, electrical, and optical properties of the ZnO thin films. As a result, 80 mTorr was optimal condition for active layer of thin film transistors, since the active layer of thin film transistors needs high resistivity to achieve low off-current and high on-off ratio. The fabricated ZnO-based thin film transistors operated in the enhancement mode with high field effect mobility and low threshold voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.222-225
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• 2008

We proposed the dry etching process recipe for the fabrication of In-Ga-Zn-O (IGZO)-based oxide TFTs, in which the etching behaviors of IGZO films were systematically investigated when the etching gas mixtures and their mixing ratios were varied. Good device characteristics of the fabricated TFT were successfully confirmed.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.374-377
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• 2009

The characteristics of the deposited thin films of the zinc oxide (ZnO) at different oxygen pressures will be elucidated in this work. The resistivity of ZnO thin films were dominated by the carrier concentration under high oxygen pressure conditions while controlled by the carrier mobility at low oxygen ambiences. In addition, we will show the characteristics of the transparent ZnO based thin film transistor (TFT) fabricated at a full room temperature process with gate dielectric of gadolinium oxide ($Gd_2O_3$) thin films.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.110.1-110.1
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• 2012

Recently, advances in ZnO based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). However, the electrical performances of oxide semiconductors are significantly affected by interactions with the ambient atmosphere. Jeong et al. reported that the channel of the IGZO-TFT is very sensitive to water vapor adsorption. Thus, water vapor passivation layers are necessary for long-term current stability in the operation of the oxide-based TFTs. In the present work, $Al_2O_3$ and $TiO_2$ thin films were deposited on poly ether sulfon (PES) and $SnO_x$-based TFTs by electron cyclotron resonance atomic layer deposition (ECR-ALD). And enhancing the WVTR (water vapor transmission rate) characteristics, barrier layer structure was modified to $Al_2O_3/TiO_2$ layered structure. For example, $Al_2O_3$, $TiO_2$ single layer, $Al_2O_3/TiO_2$ double layer and $Al_2O_3/TiO_2/Al_2O_3/TiO_2$ multilayer were studied for enhancement of water vapor barrier properties. After thin film water vapor barrier deposited on PES substrate and $SnO_x$-based TFT, thin film permeation characteristics were three orders of magnitude smaller than that without water vapor barrier layer of PES substrate, stability of $SnO_x$-based TFT devices were significantly improved. Therefore, the results indicate that $Al_2O_3/TiO_2$ water vapor barrier layers are highly proper for use as a passivation layer in $SnO_x$-based TFT devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.543-543
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• 2013

Thin-film transistors (TFTs) based on oxide semiconductors have been regarded as promising alternatives for conventional amorphous and polycrystalline silicon TFTs. Oxide TFTs have several advantages, such as low temperature processing, transparency and high field-effect mobility. Lots of oxide semiconductors for example ZnO, SnO2, In2O3, InZnO, ZnSnO, and InGaZnO etc. have been researched. Particularly, zinc-tin oxide (ZTO) is suitable for channel layer of oxide TFTs having a high mobility that Sn in ZTO can improve the carrier transport by overlapping orbital. However, some issues related to the ZTO TFT electrical performance still remain to be resolved, such as obtaining good electrical contact between source/drain (S/D) electrodes and active channel layer. In this study, the bottom-gate type ZTO TFTs with staggered structure were prepared. Thin films of ZTO (40 nm thick) were deposited by DC magnetron sputtering and performed at room temperature in an Ar atmosphere with an oxygen partial pressure of 10%. After annealing the thin films of ZTO at $400^{\circ}C$ or an hour, Cu, Mo, ITO and Ti electrodes were used for the S/D electrodes. Cu, Mo, ITO and Ti (200 nm thick) were also deposited by DC magnetron sputtering at room temperature. The channel layer and S/D electrodes were defined using a lift-off process which resulted in a fixed width W of 100 ${\mu}m$ and channel length L varied from 10 to 50 ${\mu}m$. The TFT source/drain series resistance, the intrinsic mobility (${\mu}i$), and intrinsic threshold voltage (Vi) were extracted by transmission line method (TLM) using a series of TFTs with different channel lengths. And the performances of ZTO TFTs were measured by using HP 4145B semiconductor analyzer. The results showed that the Cu S/D electrodes had a high intrinsic field effect mobility and a low effective contact resistance compared to other electrodes such as Mo, ITO and Ti.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.540-542
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• 2009

Phosphorus doped ZnO (PZO) thin films were deposited on $SiO_2$/n-Si substrates using DC magnetron sputtering system varying oxygen partial pressures from 0 to 40 % under Ar atmosphere. The deposited films showed reduced n-type conductivity due to the compensating donor effects by phosphorus dopant. The bias-time stability shows relatively good stability over bias and time comparing to un-doped ZnO-based TFTs.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.450-450
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• 2012

In recent days, advances in ZnO-based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). In particular, the development of high-mobility ZnO-based channel materials has been proven invaluable; thus, there have been many reports of high-performance TFTs with oxide semiconductor channels such as ZnO, InZnO (IZO), ZnSnO (ZTO), and InGaZnO (IGZO). The reliability of oxide TFTs can be improved by examining more stable oxide channel materials. In the present study, we investigated the effects of an ALD-deposited water vapor permeation barrier on the stability of ZnO and HfZnO (HZO) thin film transistors. The device without the water vapor barrier films showed a large turn-on voltage shift under negative bias temperature stress. On the other hand, the suitably protected device with the lowest water vapor transmission rate showed a dramatically improved device performance. As the value of the water vapor transmission rate of the barrier films was decreased, the turn-on voltage instability reduced. The results suggest that water vapor related traps are strongly related to the instability of ZnO and HfZnO TFTs and that a proper combination of water vapor permeation barriers plays an important role in suppressing the device instability.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.54.2-54.2
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• 2010

최근까지는 주로 비정질 실리콘이 디스플레이의 채널층으로 상용화 되어왔다. 비정질 실리콘 기반의 박막 트랜지스터는 제작의 경제성 및 균일성을 가지고 있어서 널리 상용화되고 있다. 하지만 비정질 실리콘의 구조적인 문제인 낮은 전자 이동도(< $1\;cm^2/Vs$)로 인하여 디스플레이의 대면적화에 부적합하며, 광학적으로 불투명한 특성을 갖기 때문에 차세대 디스플레이의 응용에 불리한 점이 있다. 이런 문제점의 대안으로 현재 국내외 여러 연구 그룹에서 산화물 기반의 반도체를 박막 트랜지스터의 채널층으로 사용하려는 연구가 진행중이다. 산화물 기반의 반도체는 밴드갭이 넓어서 광학적으로 투명하고, 상온에서 증착이 가능하며, 비정질 실리콘에 비해 월등히 우수한 이동도를 가짐으로 디스플레이의 대면적화에 유리하다. 특히 Zinc Oxide의 경우, band gap이 3.4eV로써, transparent conductors, varistors, surface acoustic waves, gas sensors, piezoelectric transducers 그리고 UV detectors 등의 많은 응용에 쓰이고 있다. 또한, a-Si TFTs에 비해 ZnO-based TFTs의 경우 우수한 소자 성능과 신뢰성을 나타내며, 대면적 제조시 우수한 균일성 및 낮은 생산비용이 장점이다. 그러나 ZnO-baesd TFTs의 경우 일정한 bias 아래에서 threshold voltage가 이동하는 문제점이 displays의 소자로 적용하는데 매우 중요하고 문제점으로 여겨진다. 특히 gate insulator와 channel layer사이의 interface에서의 defect에 의한 charge trapping이 이러한 문제점들을 야기한다고 보고되어진다. 본 연구에서는 Zinc Oxide 기반의 박막 트랜지스터를 DC magnetron sputtering을 이용하여 상온에서 제작을 하였다. 또한, $Si_3N_4$ 기판 위에 electron cyclotron resonance (ECR) $O_2$ plasma 처리와 plasma-enhanced chemical vapor deposition (PECVD)를 통하여 $SiO_2$ 를 10nm 증착을 하여 interface의 개선을 시도하였다. 그리고 TFTs 소자의 출력 특성 및 전이 특성을 평가를 하였고, 소자의 field effect mobility의 값이 향상을 하였다. 또한 Temperature, Bias Temperature stability의 조건에서 안정성을 평가를 하였다. 이러한 interface treatment는 안정성의 향상을 시킴으로써 대면적 디스플레의 적용에 비정질 실리콘을 대체할 유력한 물질이라고 생각된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.10
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• pp.648-652
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• 2014

We have investigated the effect of electrical properties of amorphous InGaZnO thin film transistors (a-IGZO TFTs) by post thermal annealing in $O_2$ ambient. The post-annealed in $O_2$ ambient a-IGZOTFT is found to be more stable to be used for oxide-based TFT devices, and has better performance, such as the on/off current ratios, sub-threshold voltage gate swing, and, as well as reasonable threshold voltage, than others do. The interface trap density is controlled to achieve the optimum value of TFT transfer and output characteristics. The device performance is significantly affected by adjusting the annealing condition. This effect is closely related with the modulation annealing method by reducing the localized trapping carriers and defect centers at the interface or in the channel layer.