• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1096-1099
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• 2004

The principal problems in development of dielectric paste materials for PDP(plasma display panel)are PbO free paste and low melting temperature. We prepared PbO free paste from glasses in the system BaO-ZnO-$B_2O_3$-$V_2O_5$. DTA, and XRD were used to characterize BaO-ZnO-$B_2O_3$-$V_2O_5$ glasses. In this present study, PbO free paste had thermal expansion of $74\times10^{-7}/^{\circ}C$, DTA softening point of $460^{\circ}C$, and firing condition of $520^{\circ}C$, 20min

• Korean Journal of Materials Research
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• v.6 no.10
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• pp.1043.1-1048
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• 1996

알루미나 매트릭스 복합재료를 AIZnMg(7075)-합금의 직접적인 용융산화를 통하여 제조하였다. 충전재료는 17$\mu\textrm{m}$ 크기의 모서리가 둥근 연마재용 SiC 입자를 사용하였다. 산화촉진재 SiO2를 사용한 경우와 사용하지 않은 경우를 비교하였다. 매트릭스 형성 매카니즘과 반응거동을 온도와 SiO2사용량을 중심으로 연구하였으며, 얻어진 AI2O3/SiC/금속 복합재료의 미세구조를 관찰하였다.

• Journal of the Korean Ceramic Society
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• v.38 no.1
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• pp.15-21
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• 2001

전자파 차폐 및 반사방지용으로 사용되는 SiO$_2$/ITO 이층박막의 전기적 특성에 미치는 전이금속이온의 영향에 대해 고찰하고 전자파 차폐이론식으로부터 박막의 전도특성에 모사하여 효과적인 전자파 차폐효과를 얻기 위한 전도막을 설계하고자 하였다. ITO 상층부에 전이금속염을 첨가한 실리카 복합졸을 코팅하여 SiO$_2$/ITO 이층막을 제조한 결과 최저 표면저항치를 나타내는 첨가량은 전이금속의 종류에 따라 차이를 보이지만 Sn 및 Zn이 첨가된 졸로부터 형성된 박막은 $10^{5}$Ω/$\square$ 이하의 낮은 저항치를 보였으며 가장 안정된 표면저하을 나타내었다. 또한 전자파 차폐효과와 전도박막의 표면저항을 차폐이론식으로부터 모사한 결과 Zn과 Sn의 전이금속염이 첨가된 SiO$_2$/ITO 투명전도막은 TCO99에서 정한 전자파 차폐기준에 부합하였다.다.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1390-1392
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• 2001

ZnO-based SAW(surface acoustic wave) filters are fabricated with the configuration of IDT/ZnO/$SiO_2$/Si(100) using various IDT materials such as Al, Cu/Ti, and Cu/Al. Their frequency response characteristics are measured and compared. The thickness of Al IDT is varied to examine the mass loading effect. In addition, effects of thermal treatment and electrical stress on the frequency responses of the fabricated SAW filters are investigated.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.70-70
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• 2011

차세대 저항 메모리로 활용 가능한 ZnO 박막의 저항 변화 특성을 평가하였다. ZnO 박막은 Pt/Ti/SiO2/Si 기판 위에 스퍼터링 시스템을 이용하여 약 50nm 두께로 증착되었다. 증착된 박막에 전극을 evaporator를 이용하여 패턴닝 함으로써 전극-반도체-전극 구조의 소자를 만들고 전기적 특성을 평가하였다. 비교적 높은 compliance current (이하Icomp)를 설정한 경우 unipolar 저항 변화특성을 나타낸 데 비해 비교적 낮은 Icomp를 설정한 경우 bipolar 저항 변화특성을 나타내었다. 두 서로 다른 저항 변화 특성은 100cycle 이상 안정적으로 재현성 있게 나타났으며 이때의 저항비는 약 $10^3$ 정도를 나타냈다. 본 결과를 바탕으로 필라멘트 이론에 기초한 저항 변화 메커니즘을 설명하는 모델이 제시되었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.540-542
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• 2009

Phosphorus doped ZnO (PZO) thin films were deposited on $SiO_2$/n-Si substrates using DC magnetron sputtering system varying oxygen partial pressures from 0 to 40 % under Ar atmosphere. The deposited films showed reduced n-type conductivity due to the compensating donor effects by phosphorus dopant. The bias-time stability shows relatively good stability over bias and time comparing to un-doped ZnO-based TFTs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.325-327
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• 2011

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a $SiO_2/Si$ substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.191-191
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• 2010

차세대 디스플레이를 위한 소자로 활용 가능한 Oxide Semiconductor TFT를 bottom gate 타입의 TFT 소자를 제작하였다. 투명 박막 트랜지스터 제작과 관련해서 ITO가 증착된 glass 기판을 gate 전극으로 사용하였고, 게이트 dielectric으로 $SiO_2/Si_3N_4$를 PECVD 방법을 사용해 증착하였으며, 채널 영역으로 ZnO를 RF magnetron sputtering을 이용하여 RF power 및 공정 압력에 따른 구조적, 광학적, 전기적 특성을 조사하였다. ZnO 박막의 공정 변수로 RF파워는 25W, 50W, 75W, 100W로 변화시키고, 증착 압력은 20m, 100m, 200m 300mTorr로 변화시켰다. Source/Drain 사이에 채널 형성 및 게이트 dielectric에서 누설전류가 TFT 특성에 미치는 영향을 연구하였다. ZnO 박막은 증착 파워 및 공정 압력에 따라 박막의 결정성이 현저하게 변화하는 것을 알 수 있었으며, 그러한 박막의 미세구조 가 TFT의 전기적인 특성에 크게 영향을 미치는 것으로 판단된다

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.235.2-235.2
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• 2015

The front transparent conductive oxide (TCO) films must exhibit good transparency, low resistivity and excellent light scattering properties for high efficiency amorphous silicon (a-Si) thin film solar cells. The light trapping phenomenon is limited due to non-uniform and low aspect ratio of the textured glass [1]. We present the low cost electrochemically deposited uniform zinc oxide (ZnO) nanorods with various aspect ratios for a-Si thin film solar cells. Since the major drawback of the electrochemically deposited ZnO nanorods was the high sheet resistance and low transmittance that was overcome by depositing the RF magnetron sputtered AZO films as a seed layer with various thicknesses [2]. The length and diameters of the ZnO nanorods was controlled by varying the deposition conditions. The length of ZnO nanorods were varied from 400 nm to $2{\mu}m$ while diameter was kept higher than 200 nm to obtain different aspect ratios. The uniform ZnO nanorods showed higher haze ratio as compared to the commercially available FTO films. We also observed that the scattering in the longer wavelength region was favored for the high aspect ratio of ZnO nanorods and much higher aspect ratios degraded the light scattering phenomenon. Therefore, we proposed our low cost and uniform ZnO nanorods for the high efficiency of thin film solar cells.