• 전기전자학회논문지
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• 제18권4호
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• pp.620-624
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• 2014

본 연구에서는, Ni/CNT/$SiO_2$ 구조의 4H-SiC MIS 캐패시터를 제작하고 전기적 특성을 조사하였다. 이를 통하여 4H-SiC MIS 소자에서 탄소나노튜브의 역할을 분석하고자 하였다. 탄소나노튜브는 이소프로필알코올과 혼합하여 $SiO_2$ 표면에 분산하였다. 소자의 전기적 특성 분석을 위하여 300-500K의 온도 범위에서 소자의 정전용량-전압 특성을 측정하였다. 밴드 평탄화 전압은 양의 방향으로 shift되었다. 정전용량-전압 그래프로부터 계면 포획 전하 밀도 및 산화막 포획 전하 밀도가 유도되었다. 산화막의 상태는 4H-SiC MIS 구조의 계면에서 전하 반송자 또는 결함 상태와 관련된다. 온도가 증가함에 따라 밴드 평탄화 전압은 음의 방향으로 shift되는 결과를 얻었다. 실험 결과로부터, Ni과 $SiO_2$ 계면에 탄소나노튜브를 첨가함에 따라 4H-SiC MIS 캐패시터의 게이트 특성을 조절 가능할 것으로 판단된다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2009년도 춘계학술대회 논문집
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• pp.879-891
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• 2009

Impedance of rails is increased by the magnetic coupling between rails and reinforcing bars in the concrete slab track. Currently, the current of track circuit has been compensated by installing the compensation capacitors on track circuit because of increasing the impedance of rails. In case of a rapid transit railway, the compensation capacitors are installed every 20[m] to compensate the current of track circuit in the concrete slab track. Because the interval of one block for a rapid transit railway is as long as 1500[m], the compensation capacitors are installed about the number of 70$\sim$75 on track circuit. However, in case the compensation capacitors are broken over the number of three, it is a problem that the amplitude of current is under standard amplitude of current which is 0.8[A]. In this paper, it was suggested installing a compensation capacitor by using resonance phenomenon on the concrete slab track. We represent the electrical model of track circuit and the four terminal network, calculate the parameters demanded for the electrical model in the concrete slab track. Also, we computed the position and capacitance of the compensation capacitor about 2040[Hz], 2400[Hz], 2760[Hz], 3120[Hz] which currently is the track circuit frequency in the Gyeongbu rapid transit railway and demonstrated the validity of it, using the Matlab and PSpice program.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권10호
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• pp.581-586
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• 2002

To improve the current waveform of diode rectifiers, we propose a new operating principle for the voltage-doubler diode rectifiers. In the conventional voltage-doubler rectifier circuit, relatively large capacitors are used to boost the output voltage, while the proposed circuit uses smaller ones and a small reactor not to boost the output voltage but improve the input current waveform. A circuit design method is shown by experimentation and confirmed simulation. The experimental results of the proposed diode rectifier satisfies the harmonic guide lines. A high input power factor of 97(%) and an efficiency of 98[%] are also obtained. The new rectifier with no controlled switches meet the harmonic guide lines, resulting in a simple, reliable and low-cost at-to dc converters in comparison with the boost-type current-improving circuits. This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance value is changed by the polarity of current or voltage. And this paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit is constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduction and the power factor improvement. Half pulse-width modulated (HPWM) inverter was explained compared with conventional pulse width modulated(PWM) inverter. Proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Advances in Energy Research
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• 제5권3호
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• pp.219-226
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• 2017

Electrochemical double layer capacitors (EDLCs) have received a tremendous interest due to their suitability for diverse applications. They have been fabricated using different carbon based electrodes including activated carbons, single walled/multi walled carbon nano tubes. But, graphite which is one of the natural resources in Sri Lanka has not been given a considerable attention towards using for EDLCs though it is a famous carbon material. On the other hand, EDLCs are well reported with various liquid electrolytes which are associated with numerous drawbacks. Gel polymer electrolytes (GPE) are well known alternative for liquid electrolytes. In this paper, it is reported about an EDLC fabricated with a nano composite polyethylene oxide based GPE and two Sri Lankan graphite based electrodes. The composition of the GPE was [{(10PEO: $NaClO_4$) molar ratio}: 75wt.% PC] : 5 wt.% $TiO_2$. GPE was prepared using the solvent casting method. Two graphite electrodes were prepared by mixing 85% graphite and 15% polyvinylidenefluoride (PVdF) in acetone and casting n fluorine doped tin oxide glass plates. GPE film was sandwiched in between the two graphite electrodes. A non faradaic charge discharge mechanism was observed from the Cyclic Voltammetry study. GPE was stable in the potential windows from (-0.8 V-0.8 V) to (-1.5 V-1.5 V). By increasing the width of the potential window, single electrode specific capacity increased. Impedance plots confirmed the capacitive behavior at low frequency region. Galvanostatic charge discharge test yielded an average discharge capacity of $0.60Fg^{-1}$.

• 한국재료학회지
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• 제24권1호
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• pp.37-42
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• 2014

Well-distributed ruthenium (Ru) nanoparticles decorated on porous carbon nanofibers (CNFs) were synthesized using an electrospinning method and a reduction method for use in high-performance elctrochemical capacitors. The formation mechanisms including structural, morphological, and chemical bonding properties are demonstrated by means of field emission scanning electron microscopy (FESEM), transmission electron microscopy (TEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS). To investigate the optimum amount of the Ru nanoparticles decorated on the porous CNFs, we controlled three different weight ratios (0 wt%, 20 wt%, and 40 wt%) of the Ru nanoparticles on the porous CNFs. For the case of 20 wt% Ru nanoparticles decorated on the porous CNFs, TEM results indicate that the Ru nanoparticles with ~2-4 nm size are uniformly distributed on the porous CNFs. In addition, 40 wt% Ru nanoparticles decorated on the porous CNFs exhibit agglomerated Ru nanoparticles, which causes low performance of electrodes in electrochemical capacitors. Thus, proper distribution of 20 wt% Ru nanoparticles decorated on the porous CNFs presents superior specific capacitance (~280.5 F/g at 10 mV/s) as compared to the 40 wt% Ru nanoparticles decorated on the porous CNFs and the only porous CNFs. This enhancement can be attributed to the synergistic effects of well-distributed Ru nanoparticles and porous CNF supports having high surface area.

• 전력전자학회논문지
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• 제8권6호
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• pp.469-477
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• 2003

본 논문은 플라잉 커패시터 멀티-레벨 인버터의 가장 큰 문제점인 플라잉 커패시터 전압 불균형의 새로운 해결방법으로 캐리어 로테이션(Carrier-Rotation) PWM 기법을 제안한다. 제안된 기법은 모든 스위치가 한번의 스위칭동작을 하는 동안 플라잉 커패시터의 충전과 방전에 관계된 레그 전압 리던던시(redundancy)를 같은 비율로 사용하여 플라잉 커패시터 전압을 일정하게 유지하며, 전압의 변동폭이 최소가 되도록 제어한다 이 방법은 각 캐리어의 배치가 모두 통상이므로 출력 전압의 고조파 성분이 저감되며, 또한 모든 스위치의 스위칭 주파수가 같으므로 스위치 이용률이 개선되는 특성을 갖는다. 제안된 기법을 플라잉 커패시터 3-레벨 인버터에 적용하여 상세히 분석하고, 3-레벨 이상에 적용할 수 있도록 일반화한다. 제안된 기법의 타당성은 실험 결과로 검증된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.45-45
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• 2007

Capacitors among the embedded passive components are most widely studied because they are the major components in terms of size and number and hard to embed compared with resistors and inductors due to the more complicated structure. To fabricate a capacitor-embedded PCB for in-line process, it is essential to adopt a low temperature process (<$200^{\circ}C$). However, high dielectric materials such as ferroelectrics show a low permittivity and a high dielectric loss when they are processed at low temperatures. To solve these contradicting problems, we studied BMN materials as a candidate for dielectric capacitors. processed at PCB-compatible temperatures. The morphologies of BMN thin films were investigated by AFM and SEM equipment. The electric properties (C-F, I-V) of Pt/BMN/Cu/polymer were evaluated using an impedance analysis (HP 4194A) and semiconductor parameter analyzer (HP4156A). $Bi_2Mg_{2/3}Nb_{4/3}O_7$(BMN) thin films deposited on copper clad laminate substrates by sputtering system as a function of Ar/$O_2$ flow rate at room temperature showed smooth surface morphologies having root mean square roughness of approximately 5.0 nm. 200-nm-thick films deposited at RT exhibit a dielectric constant of 40, a capacitance density of approximately $150\;nF/cm^2$, and breakdown voltage above 6 V. The crystallinity of the BMN thin films was studied by TEM and XRD. BMN thin film capacitors are expected to be promising candidates as embedded capacitors for printed circuit board (PCB).

• 한국재료학회지
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• 제11권2호
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• pp.151-154
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• 2001

상부전극, Pt, Ir, 그리고 $IrO_2$, 에 따라 수소 열처리전과 후, 그리고 회복열처리시 누설전류특성을 고찰하였다. Pt/PLZT/Pt 케페시터는 수소열처리 후에 다시 회복열처리를 수행하면 완전히 이력곡선의 회복을 보이며 또한 피로특성도 거의 회복 된다. Pt과 IrO$_2$ 상부전극의 경우의 진 누설전류 특성은 열처리조건에 관계없이 강한 시간 의존성을 갖는 space-charge influenced injection모델에 적합하다. 반면에 Ir 상부전극의 경우는 Ir과 PLZT 사이의 계면에 헝성된 전도성 상인 $IrO_2$로 인해 높은 누설전류 밀도를 보이면서 relaxation current 영역이 없이 steady state 영역을 보이는, 주로 Schottky barrier 모델에 의해 설명된다.

• Transactions on Electrical and Electronic Materials
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• 제5권1호
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• pp.19-23
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• 2004

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1587-1588
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• 2006

Tn this paper, PCB (Printed Circuit Board) embedded $BaTiO_3$ MIM capacitors were designed, fabricated, and characterized for low cost organic SOP applications by using 3-D EM simulator and low temperature processes. Size of electrodes and thickness of high dielectric films are optimized for improving the performance characteristics of the proposed embedded MIM capacitors at high frequency regime. The selected thicknesses of the $BaTiO_3$ film are $12{\mu}m$, $16{\mu}m$, and $20{\mu}m$. The fabricated MIM capacitor with dielectric constant of 30 and thickness of $12{\mu}m$ has capacitance density of $21.5p\;F/mm^2$ at 100MHz, maximum quality factor of 37.4 at 300 MHz, a quality factor of 30.9 at 1GHz, self resonant frequency of 5.4 GHz, respectively. The measured capacitances and quality factors are well matched with 3-D EM simulated ones. These embedded capacitors are promising for SOP based advanced electronic systems with various functionality, low cost, small size and volume.