• Journal of IKEEE
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• v.18 no.4
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• pp.620-624
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• 2014

In this study, the electrical characteristics of Ni/CNT/$SiO_2$ structures were investigated in order to analyze the mechanism of carbon nanotubes in 4H-SiC MIS device structures. We fabricated 4H-SiC MIS capacitors with or without carbon nanotubes. Carbon nanotubes were dispersed by isopropyl alcohol. The capacitance-voltage (C-V) is characterized at 300 to 500K. The experimental flat-band voltage ($V_{FB}$) shift was positive. Near-interface trapped charge density and oxide trapped charge density values of Ni/CNT/$SiO_2$ structure were less than values of reference samples. With increasing temperature, the flat-band voltage was negative. It has been found that its oxide quality is related to charge carriers or defect states in the interface of 4H-SiC MIS capacitors. Gate characteristics of 4H-SiC MIS capacitors can be controlled by carbon nanotubes between Ni and $SiO_2$.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.879-891
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• 2009

Impedance of rails is increased by the magnetic coupling between rails and reinforcing bars in the concrete slab track. Currently, the current of track circuit has been compensated by installing the compensation capacitors on track circuit because of increasing the impedance of rails. In case of a rapid transit railway, the compensation capacitors are installed every 20[m] to compensate the current of track circuit in the concrete slab track. Because the interval of one block for a rapid transit railway is as long as 1500[m], the compensation capacitors are installed about the number of 70$\sim$75 on track circuit. However, in case the compensation capacitors are broken over the number of three, it is a problem that the amplitude of current is under standard amplitude of current which is 0.8[A]. In this paper, it was suggested installing a compensation capacitor by using resonance phenomenon on the concrete slab track. We represent the electrical model of track circuit and the four terminal network, calculate the parameters demanded for the electrical model in the concrete slab track. Also, we computed the position and capacitance of the compensation capacitor about 2040[Hz], 2400[Hz], 2760[Hz], 3120[Hz] which currently is the track circuit frequency in the Gyeongbu rapid transit railway and demonstrated the validity of it, using the Matlab and PSpice program.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.10
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• pp.581-586
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• 2002

To improve the current waveform of diode rectifiers, we propose a new operating principle for the voltage-doubler diode rectifiers. In the conventional voltage-doubler rectifier circuit, relatively large capacitors are used to boost the output voltage, while the proposed circuit uses smaller ones and a small reactor not to boost the output voltage but improve the input current waveform. A circuit design method is shown by experimentation and confirmed simulation. The experimental results of the proposed diode rectifier satisfies the harmonic guide lines. A high input power factor of 97(%) and an efficiency of 98[%] are also obtained. The new rectifier with no controlled switches meet the harmonic guide lines, resulting in a simple, reliable and low-cost at-to dc converters in comparison with the boost-type current-improving circuits. This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance value is changed by the polarity of current or voltage. And this paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit is constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduction and the power factor improvement. Half pulse-width modulated (HPWM) inverter was explained compared with conventional pulse width modulated(PWM) inverter. Proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Advances in Energy Research
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• v.5 no.3
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• pp.219-226
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• 2017

Electrochemical double layer capacitors (EDLCs) have received a tremendous interest due to their suitability for diverse applications. They have been fabricated using different carbon based electrodes including activated carbons, single walled/multi walled carbon nano tubes. But, graphite which is one of the natural resources in Sri Lanka has not been given a considerable attention towards using for EDLCs though it is a famous carbon material. On the other hand, EDLCs are well reported with various liquid electrolytes which are associated with numerous drawbacks. Gel polymer electrolytes (GPE) are well known alternative for liquid electrolytes. In this paper, it is reported about an EDLC fabricated with a nano composite polyethylene oxide based GPE and two Sri Lankan graphite based electrodes. The composition of the GPE was [{(10PEO: $NaClO_4$) molar ratio}: 75wt.% PC] : 5 wt.% $TiO_2$. GPE was prepared using the solvent casting method. Two graphite electrodes were prepared by mixing 85% graphite and 15% polyvinylidenefluoride (PVdF) in acetone and casting n fluorine doped tin oxide glass plates. GPE film was sandwiched in between the two graphite electrodes. A non faradaic charge discharge mechanism was observed from the Cyclic Voltammetry study. GPE was stable in the potential windows from (-0.8 V-0.8 V) to (-1.5 V-1.5 V). By increasing the width of the potential window, single electrode specific capacity increased. Impedance plots confirmed the capacitive behavior at low frequency region. Galvanostatic charge discharge test yielded an average discharge capacity of $0.60Fg^{-1}$.

• Korean Journal of Materials Research
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• v.24 no.1
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• pp.37-42
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• 2014

Well-distributed ruthenium (Ru) nanoparticles decorated on porous carbon nanofibers (CNFs) were synthesized using an electrospinning method and a reduction method for use in high-performance elctrochemical capacitors. The formation mechanisms including structural, morphological, and chemical bonding properties are demonstrated by means of field emission scanning electron microscopy (FESEM), transmission electron microscopy (TEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS). To investigate the optimum amount of the Ru nanoparticles decorated on the porous CNFs, we controlled three different weight ratios (0 wt%, 20 wt%, and 40 wt%) of the Ru nanoparticles on the porous CNFs. For the case of 20 wt% Ru nanoparticles decorated on the porous CNFs, TEM results indicate that the Ru nanoparticles with ~2-4 nm size are uniformly distributed on the porous CNFs. In addition, 40 wt% Ru nanoparticles decorated on the porous CNFs exhibit agglomerated Ru nanoparticles, which causes low performance of electrodes in electrochemical capacitors. Thus, proper distribution of 20 wt% Ru nanoparticles decorated on the porous CNFs presents superior specific capacitance (~280.5 F/g at 10 mV/s) as compared to the 40 wt% Ru nanoparticles decorated on the porous CNFs and the only porous CNFs. This enhancement can be attributed to the synergistic effects of well-distributed Ru nanoparticles and porous CNF supports having high surface area.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.6
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• pp.469-477
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• 2003

This paper proposes a Carrier-Rotation (CR) PWM technique that is a new solution for the voltage unbalancing problem of flying capacitors in the Flying Capacitor Multi-level Inverter (FCMI). The proposed technique equalizes the utilization of phase leg voltage redundancies corresponding to the charging and the discharging state of individual flying capacitors during each switching period of all the switches. Therefore, the charging and the discharging quantity of flying capacitors are equal, which makes the average variation of flying capacitor voltages become zero and keeps their voltage stable during minimum specified period. It also has the reduced harmonic contents of output voltage and the same switch utilization since all the carrier signals are in phase and the switching frequency of each switch is identical. The proposed technique is analyzed precisely in flying capacitor 3-level inverter and then it has expanded to the FCMI (N-level, N>3). Experimental results on the laboratory prototype flying capacitor 3-level inverter confirm the validity of the proposed technique.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.45-45
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• 2007

Capacitors among the embedded passive components are most widely studied because they are the major components in terms of size and number and hard to embed compared with resistors and inductors due to the more complicated structure. To fabricate a capacitor-embedded PCB for in-line process, it is essential to adopt a low temperature process (<$200^{\circ}C$). However, high dielectric materials such as ferroelectrics show a low permittivity and a high dielectric loss when they are processed at low temperatures. To solve these contradicting problems, we studied BMN materials as a candidate for dielectric capacitors. processed at PCB-compatible temperatures. The morphologies of BMN thin films were investigated by AFM and SEM equipment. The electric properties (C-F, I-V) of Pt/BMN/Cu/polymer were evaluated using an impedance analysis (HP 4194A) and semiconductor parameter analyzer (HP4156A). $Bi_2Mg_{2/3}Nb_{4/3}O_7$(BMN) thin films deposited on copper clad laminate substrates by sputtering system as a function of Ar/$O_2$ flow rate at room temperature showed smooth surface morphologies having root mean square roughness of approximately 5.0 nm. 200-nm-thick films deposited at RT exhibit a dielectric constant of 40, a capacitance density of approximately $150\;nF/cm^2$, and breakdown voltage above 6 V. The crystallinity of the BMN thin films was studied by TEM and XRD. BMN thin film capacitors are expected to be promising candidates as embedded capacitors for printed circuit board (PCB).

• Korean Journal of Materials Research
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• v.11 no.2
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• pp.151-154
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• 2001

The leakage current behaviors of PLZT capacitors with top electrodes of Pt, Ir, and $IrO_2$ are investigated before and after hydrogen forming gas anneal. The P-E hysteresis and fatigue properties of Pt/PLZT/Pt capacitors are almost recovered after recovery anneal in $O_2$ ambient. The leakage current mechanisms of PLZT capacitors with Pt and $IrO_2$ top electrodes are consistent with space-charge influenced injection model showing the strong time dependence irrespective of annealing conditions. On the other hand, the leakage current behavior of Ir/PLZT/Pt capacitor shows steady state independent of time because IrPb, conducting phase, formed at interface between Ir top and PLZT is a high conduction path. Teh leakage current mechanism of Ir/PLZT/Pt capacitor is consistent with Schottky barrier model.

• Transactions on Electrical and Electronic Materials
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• v.5 no.1
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• pp.19-23
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• 2004

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1587-1588
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• 2006

Tn this paper, PCB (Printed Circuit Board) embedded $BaTiO_3$ MIM capacitors were designed, fabricated, and characterized for low cost organic SOP applications by using 3-D EM simulator and low temperature processes. Size of electrodes and thickness of high dielectric films are optimized for improving the performance characteristics of the proposed embedded MIM capacitors at high frequency regime. The selected thicknesses of the $BaTiO_3$ film are $12{\mu}m$, $16{\mu}m$, and $20{\mu}m$. The fabricated MIM capacitor with dielectric constant of 30 and thickness of $12{\mu}m$ has capacitance density of $21.5p\;F/mm^2$ at 100MHz, maximum quality factor of 37.4 at 300 MHz, a quality factor of 30.9 at 1GHz, self resonant frequency of 5.4 GHz, respectively. The measured capacitances and quality factors are well matched with 3-D EM simulated ones. These embedded capacitors are promising for SOP based advanced electronic systems with various functionality, low cost, small size and volume.