• Title/Summary/Keyword: XOR Operation

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All-Optical Composite Logic Gates with XOR, NOR, OR, and NAND Functions using Parallel SOA-MZI Structures (병렬 SOA-MZI 구조들을 이용한 XOR, NOR, OR 그리고 NAND 기능들을 가진 전광 복합 논리 게이트들)

  • Kim Joo-Youp;Han Sang-Kook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.1 s.343
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    • pp.13-16
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    • 2006
  • We have proposed and experimentally demonstrated the all-optical composite logic gates with XOR, NOR, OR and NAND functions using SOA-MZI structures to make it possible to simultaneously perform various logical functions. The proposed scheme is robust and feasible for high speed all-optical logic operation with high ER.

An Implementation on the XOR-ACC of Multimedia Fingerprinting using Neural Network (신경망을 이용한 멀티미디어 핑거프린팅의 XOR-ACC 구현)

  • Rhee, Kang-Hyeon
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.48 no.6
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    • pp.1-8
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    • 2011
  • In multimedia fingerprinting field, it is many used a code based on BIBD, which has a strong resiliency of anti-collusion. When a collusion-attack code is generated with a logical XOR operation using the code based on BIBD, then some cases are occurred that a colluded code could be generated to the same fingerprint of non-colluder on the other hand, the colluder is decided to the non-colluder so that he would be excepted in the colluder tracing. For solving the serious problem of the wrong decision of the colluder tracing in this paper, XOR-ACC is implemented using multi-layer perceptron neural network among (AND, OR, XOR and Averaging)-ACC by the measured correlation coefficient. Through the experiment, it confirms that XOR-ACC efficiency of multimedia fingerprinting code{7,3,1} based on BIBD is improved to 88.24% from the conventional 41.18%, so that a ratio of the colluder tracing is also improved to 100% from the conventional 53%. As a result, it could be traced and decided completely a sectional colluder and non-colluder about the collusion attacks.

Design and Demonstration of All-Optical XOR, AND, OR Gate in Single Format by Using Semiconductor Optical Amplifiers (반도체 광증폭기를 이용한 다기능 전광 논리 소자의 설계 및 측정)

  • Son, Chang-Wan;Yoon, Tae-Hoon;Kim, Sang-Hun;Jhon, Young-Min;Byun, Yung-Tae;Lee, Seok;Woo, Deok-Ha;Kim, Sun-Ho
    • Korean Journal of Optics and Photonics
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    • v.17 no.6
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    • pp.564-568
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    • 2006
  • Using the cross-gain modulation (XGM) characteristics of semiconductor optical amplifiers (SOAs), multi-functional all-optical logic gates, including XOR, AND, and OR gates are successfully simulated and demonstrated at 10Gbit/s. A VPI component maker^TM simulation tool is used for the simulation of multi-functional all-optical logic gates and the10 Cbit/s input signal is made by a mode-locked fiber ring laser. A multi-quantum well (MQW) SOA is used for the simulation and demonstration of the all-optical logic system. Our suggested system is composed of three MQW SOAs, SOA-1 and SOA-2 for XOR logic operation and SOA-2 and SOA-3 for AND logic operation. By the addition of two output signals XOR and AND, all-optical OR logic can be obtained.

Hierarchial Encryption System Using Two-Step Phase-Shifting Digital Holography Technology Based on XOR and Scramble Operations (XOR 및 스크램블 연산 기반 2단계 위상 천이 디지털 홀로그래피 기술을 이용한 계층적 암호화 시스템)

  • Kim, Cheolsu
    • Journal of Korea Multimedia Society
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    • v.25 no.8
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    • pp.983-990
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    • 2022
  • In this paper, we implemented a hierarchical encryption system using two-step phase-shifting digital holography(PSDH) technology based on XOR and scramble operations. The proposed encryption system is a system that authenticates access through the issuance of an encryption key for access to individual laboratories, department offices, and universities. In the encryption process, we proposed a double encryption method using XOR and scramble operation with digital technology and two-step phase-shifting digital holography with optical technology. In the two-step PSDH process, an new method of determining the reference wave intensity without measuring it by using random common object image gererated from digital encryption process was also proposed. In the decryption process, the process is performed in the reverse order of encryption process. And only when the various key information used in the encryption process is correct, the encrypted information can be decrypted, so that the user can access the desired place. That is, there is a feature that can hierarchically control the space that can be accessed according to the type of key issued in the proposed encryption system. Through the computer simulation, the feasibility of the proposed hierarchical encryption system was confirmed.

Optical Implementation of Triple DES Algorithm Based on Dual XOR Logic Operations

  • Jeon, Seok Hee;Gil, Sang Keun
    • Journal of the Optical Society of Korea
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    • v.17 no.5
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    • pp.362-370
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    • 2013
  • In this paper, we propose a novel optical implementation of a 3DES algorithm based on dual XOR logic operations for a cryptographic system. In the schematic architecture, the optical 3DES system consists of dual XOR logic operations, where XOR logic operation is implemented by using a free-space interconnected optical logic gate method. The main point in the proposed 3DES method is to make a higher secure cryptosystem, which is acquired by encrypting an individual private key separately, and this encrypted private key is used to decrypt the plain text from the cipher text. Schematically, the proposed optical configuration of this cryptosystem can be used for the decryption process as well. The major advantage of this optical method is that vast 2-D data can be processed in parallel very quickly regardless of data size. The proposed scheme can be applied to watermark authentication and can also be applied to the OTP encryption if every different private key is created and used for encryption only once. When a security key has data of $512{\times}256$ pixels in size, our proposed method performs 2,048 DES blocks or 1,024 3DES blocks cipher in this paper. Besides, because the key length is equal to $512{\times}256$ bits, $2^{512{\times}256}$ attempts are required to find the correct key. Numerical simulations show the results to be carried out encryption and decryption successfully with the proposed 3DES algorithm.

A New Approach to the Synthesis of Two-Dimensional Cellular Arrays Using Internal Don't Cares (내부 Dont't care를 이용한 이차원 셀 배열의 새로운 합성 방법)

  • Lee, Dong-Geon;Jeong, Mi-Gyeong;Lee, Gwi-Sang
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.49 no.2
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    • pp.81-87
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    • 2000
  • This paper presents a new approach to the synthesis of two-dimensional arrays such as Atmel 6000 series FPGAs using internal don't cares. Basically complex terms which fits to the linear array of cells without further routing wires are generated and they are collected by OR/XOR operations. In previous methods, complex terms are collected only by XOR operations, which may not be effective for nearly unate functions. In this paper, we allow complex terms to be collected by OR operations in addition to XOR operations. First, complex terms that lies in the ON-set of the function are generated and collected by OR operations. The sub-function realized by the first stage becomes an internal don't cares and they are exploited in the second stage which generates complex terms collectable by XOR operation. Experimental results shows the efficacy of the proposed method compared to the previous methods.

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Low System Complexity Parallel Multiplier for a Class of Finite Fields based on AOP (시스템 복잡도 개선을 위한 AOP 기반의 병렬 유한체 승산기)

  • 변기영;나기수;윤병희;최영희;한성일;김흥수
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.3A
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    • pp.331-336
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    • 2004
  • This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2$^{m}$ ). From the properties of an irreducible AOP of degree m. the modular reduction in GF(2$^{m}$ ) multiplicative operation can be simplified using cyclic shift operation. And then, GF(2$^{m}$ ) multiplicative operation can be established using the away structure of AND and XOR gates. The proposed multiplier is composed of m(m+1) 2-input AND gates and (m+1)$^2$ 2-input XOR gates. And the minimum critical path delay is Τ$_{A+}$〔lo $g_2$$^{m}$ 〕Τ$_{x}$ proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.n.

Optical System Implementation of OFB Block Encryption Algorithm (OFB 블록 암호화 알고리즘의 광학적 시스템 구현)

  • Gil, Sang-Keun
    • Journal of IKEEE
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    • v.18 no.3
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    • pp.328-334
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    • 2014
  • This paper proposes an optical encryption and decryption system for OFB(Output Feedback Block) encryption algorithm. The proposed scheme uses a dual-encoding technique in order to implement optical XOR logic operation. Also, the proposed method provides more enhanced security strength than the conventional electronic OFB method due to the huge security key with 2-dimensional array. Finally, computer simulation results of encryption and decryption are shown to verify the proposed method, and hence the proposed method makes it possible to implement more effective and stronger optical block encryption system with high-speed performance and the benefits of parallelism.

Solder Paste Pattern Classification Using the XOR Operation in Vision Inspection Machines (비젼 검사시스템에서 XOR연산을 이용한 납땜형상의 패턴분류)

  • Lee, Chang-Gil;Hwang, Jung-Ho;Kim, Min-Soo
    • Proceedings of the KIEE Conference
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    • 2001.07d
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    • pp.2735-2737
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    • 2001
  • 비젼 검사시스템에서 기판에 존재하는 납 형상의 패턴을 분류함으로써 사전에 불량을 줄일 수 있다. 이러한 경우 대부분의 불량은 부정확한 납의 위치 및 두께로 인해 발생하게 되는데, 이러한 문제를 해결하기 위해 주어진 경계 내에 불분명하게 형성된 납의 형태 및 두께를 정상과 불량으로 분류하기 위해 무게중심점에 기초한 정합과 XOR연산을 이용한 비젼 검사시스템을 제안하였다. 제안한 비젼 검사시스템을 인쇄회로기판상의 납땜형상 패턴에 적용하여 제안한 방법의 성능을 검증하였다.

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All-Optical Binary Full Adder Using Logic Operations Based on the Nonlinear Properties of a Semiconductor Optical Amplifier

  • Kaur, Sanmukh;Kaler, Rajinder-Singh;Kamal, Tara-Singh
    • Journal of the Optical Society of Korea
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    • v.19 no.3
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    • pp.222-227
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    • 2015
  • We propose a new and potentially integrable scheme for the realization of an all-optical binary full adder employing two XOR gates, two AND gates, and one OR gate. The XOR gate is realized using a Mach-Zehnder interferometer (MZI) based on a semiconductor optical amplifier (SOA). The AND and OR gates are based on the nonlinear properties of a semiconductor optical amplifier. The proposed scheme is driven by two input data streams and a carry bit from the previous less-significant bit order position. In our proposed design, we achieve extinction ratios for Sum and Carry output signals of 10 dB and 12 dB respectively. Successful operation of the system is demonstrated at 10 Gb/s with return-to-zero modulated signals.