• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.1406-1407
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• 2009

본 연구에서는 하드웨어적으로 제한사항이 있는 장비에서 최소한의 보안성을 제공하기 위해 XOR 방식의 Pair-wise 키값을 생성하는 간단한 보안기법을 제안한다. 제안한 보안 기법은 Random Key Predistribution 을 통하여 장비별 시간값과 고유값을 XOR 하여 서로 교환한 후, 상호 교환한 값을 다시 XOR 하여 두 장비간의 Pair-wise 키값을 생성한다. 이후, 지속적으로 변화되는 시간값으로 인해 매 통신시마다 다른 Pair-wise 키값을 사용할 수 있을 것이다. 기존의 보안알고리즘(DES, AES 등)의 연산 보다 매우 간단하고, 노드별 독특한 키 변화패턴을 통하여 키 유출이 어려우며, 장비가 캡처당하는 공격이 발생하더라도 전체 네트워크의 보안성이 저하되지 않는다는 장점을 가진다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.6
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• pp.1-7
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• 2010

This paper presents a novel implementation on multimedia fingerprinting algorithm based on BCH (Bose-Chaudhuri-Hocquenghem) code. The evaluation is put in force the colluder detection to n-1. In the proposed algorit hm, the used collusion attacks adopt logical combinations (AND, OR and XOR) and average computing (Averaging). The fingerprinting code is generated as below step: 1. BIBD {7,4,1} code is generated with incidence matrix. 2. A new encoding method namely combines BIBD code with BCH code, these 2 kind codes are to be fingerprinting code by BCH encoding process. 3. The generated code in step 2, which would be fingerprinting code, that characteristic is similar BCH {15,7} code. 4. With the fingerprinting code in step 3, the collusion codebook is constructed for the colluder detection. Through an experiment, it confirmed that the ratio of colluder detection is 86.6% for AND collusion, 32.8% for OR collusion, 0% for XOR collusion and 66.4% for Averaging collusion respectively. And also, XOR collusion could not detect entirely colluder and on the other hand, AND and Averaging collusion could detect n-1 colluders and OR collusion could detect k colluders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3C
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• pp.286-292
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• 2006

Both composition and XOR are operations widely used to enhance security of cryptographic schemes. The more number of random permutations we compose (resp. XOR), the more secure random permutation (resp. random function) we get. Combining the two methods, we consider a generalized form of random function: $SUM^s - CMP^c = ({\pi}_{sc} ... {\pi}_{(s-1)c+1}){\oplus}...{\oplus}({\pi}_c...{\pi}_1)$ where ${\pi}_1...{\pi}_{sc}$ are random permutations. Given a fixed number of random permutations, there seems to be a trade-off between composition and XOR for security of $SUM^s - CMP^c$. We analyze this trade-off based on some upper bound of insecurity of $SUM^s - CMP^c$, and investigate what the optimal number of each operation is, in order to lower the upper bound.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.389-389
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• 2006

• Journal of the Korea Society of Computer and Information
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• v.19 no.10
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• pp.81-89
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• 2014

In this paper, we propose SA hash algorithm to avoid upload identical files and design server system using proposed SA hash algorithm. Client to want to upload file examines the value of SA hash and if the same file is found in server system client use the existing file without upload. SA hash algorithm which is able to examine the identical-file divides original file into blocks of n bits. Original file's mod i bit and output hash value's i bit is calculated with XOR operation. It is SA hash algorithm's main routine to repeat the calculation with XOR until the end of original file. Using SA hash algorithm which is more efficient than MD5, SHA-1 and SHA-2, we can design server system to avoid uploading identical file and save storage capacity and upload-time of server system.

• Journal of IKEEE
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• v.19 no.3
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• pp.288-294
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• 2015

CRC function has been built into the high-speed semiconductor memory device in order to increase the reliability of data for high-speed operation. Also, DBI function is adopted to improve of data transmission speed. Conventional CRC(ATM-8 HEC code) method has a significant amounts of area-overhead(~XOR 700 gates), and processing time(6 stage XOR) is large. Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC calculations. In this paper, we propose a CRC method for low cost and high speed memory, which was improved 92% for area-overhead. For low-cost implementation of the CRC scheme by the DBI function it was supplemented by data bit error detection rate. And analyzing the error detection rate were compared with conventional CRC method.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.24-30
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• 2003

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.

• Journal of IKEEE
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• v.18 no.4
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• pp.509-516
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• 2014

CRC feature in a high-speed semiconductor memory devices such as DDR4/GDDR5 increases the data reliability. Conventional CRC method have a massive area overhead and long delay time. It leads to insufficient internal timing margins for CRC calculation. This paper, presents a CRC code method that provides error detection and a real-time matrix type CRC. If there are errors in the data, proposed method can alert to the system in a real-time manner. Compare to the conventional method(XOR 6 stage ATM-8 HEC code), the proposing method can improve the error detection circuits up to 60% and XOR stage delay by 33%. Also the real-time error detection scheme can improve the error detection speed to agerage 50% for the entire data bits(UI0~UI9).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.331-336
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• 2004

This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2$^{m}$ ). From the properties of an irreducible AOP of degree m. the modular reduction in GF(2$^{m}$ ) multiplicative operation can be simplified using cyclic shift operation. And then, GF(2$^{m}$ ) multiplicative operation can be established using the away structure of AND and XOR gates. The proposed multiplier is composed of m(m+1) 2-input AND gates and (m+1)$^2$ 2-input XOR gates. And the minimum critical path delay is Τ$_{A+}$〔lo $g_2$$^{m}$ 〕Τ$_{x}$ proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.n.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.6
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• pp.1443-1454
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• 2016

Balanced encoding method that implement Dual-rail logic style based on hardware technique to software is efficient countermeasure against side-channel analysis without additional memory. Since balanced encoding keep Hamming weight and/or Hamming distance of intermediate values constantly, using this method can be effective as countermeasure against side channel analysis due to elimination of intermediate values having HW and/or HD relating to secret key. However, former studies were presented for Constant XOR operation, which can only be applied to crypto algorithm that can be constructed XOR operation, such as PRINCE. Therefore, our first proposal of new Constant ADD, Shift operations can be applied to various symmetric crypto algorithms based on ARX. Moreover, we did not used look-up table to obtain efficiency in memory usage. Also, we confirmed security of proposed Constant operations with Mutual Information Analysis.