• ETRI Journal
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• v.33 no.2
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• pp.230-239
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• 2011

Dynamic memory allocators for real-time embedded systems need to fulfill three fundamental requirements: bounded worst-case execution time, fast average execution time, and minimal fragmentation. Since embedded systems generally run continuously during their whole lifetime, fragmentation is one of the most important factors in designing the memory allocator. This paper focuses on minimizing fragmentation while other requirements are still satisfied. To minimize fragmentation, a part of a memory region is segregated by the proposed budgeting method that exploits the memory profile of the given application. The budgeting method can be applied for any existing memory allocators. Experimental results show that the memory efficiency of allocators can be improved by up to 18.85% by using the budgeting method. Its worst-case execution time is analyzed to be bounded.

• Journal of Computing Science and Engineering
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• v.7 no.1
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• pp.67-80
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• 2013

The worst-case execution time (WCET) of each real-time task in multicore processors with shared caches can be significantly affected by inter-thread cache interferences. The worst-case inter-thread cache interferences are dependent on how tasks are scheduled to run on different cores. Therefore, there is a circular dependence between real-time task scheduling, the worst-case inter-thread cache interferences, and WCET in multicore processors, which is not the case for single-core processors. To address this challenging problem, we present an offline real-time scheduling approach for multicore processors by considering the worst-case inter-thread interferences on shared L2 caches. Our scheduling approach uses a greedy heuristic to generate safe schedules while minimizing the worst-case inter-thread shared L2 cache interferences and WCET. The experimental results demonstrate that the proposed approach can reduce the utilization of the resulting schedule by about 12% on average compared to the cyclic multicore scheduling approaches in our theoretical model. Our evaluation indicates that the enhanced scheduling approach is more likely to generate feasible and safe schedules with stricter timing constraints in multicore real-time systems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.866-874
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• 2006

This paper proposes a new Dynamic Voltage Scaling(DVS) algorithm to achieve low-power scheduling of aperiodic hard real-time tasks. Aperiodic tasks schedulingcannot be applied to the conventional DVS algorithm and result in consuming energy more than periodic tasks because they have no period, non predictable worst case execution time, and release time. In this paper, we defined Virtual Periodic Task Set(VTS) which has constant period and worst case execution time, and released aperiodic tasks are assigned to this VTS. The period and worst case execution time of the virtual task can be obtained by calculating task utilization rate of both periodic and aperiodic tasks. The proposed DVS algorithm scales the frequency of both periodic and aperiodic tasks in VTS. Simulation results show that the energy consumption of the proposed algorithm is reduced by 11% over the conventional DVS algorithm for only periodic task.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.11
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• pp.601-610
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• 2002

Intra-task voltage scheduling (IntraVS), which adjusts the supply voltage within an individual task boundary, is an effective technique for developing low-power applications. In this paper, we propose a novel intra-task voltage scheduling algorithm for hard real-time applications based on average-case execution time. Unlike the conventional IntraVS algorithm where voltage scaling decisions are based on the worst-case execution cycles, tile proposed algorithm improves the energy efficiency by controlling the execution speed based on average-case execution cycles while meeting the real-time constraints. The experimental results using an MPEG-4 decoder program show that the proposed algorithm reduces the energy consumption by up to 34% over conventional IntraVS algorithm.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1379-1382
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• 2003

Recently, mobile embedded systems used widly in various applications. Managing power consumption is becoming a matter of primary concern because those systems use limited power supply. As an approach reduce power consumption, voltage can be scaled down. according to the execution time and deadline. By reducing the supplying voltage to 1/N power consumption can be reduced to 1/N. DPM-S is a well known method for dynamic voltage scaling. In this paper, we enhanced DPM-S by using average execution time aggressively. The frequency of processor is calculated based in average execution time instead of worst case execution time. Simulation results show that our method achieve up to 5％ energy savings than DPM-S.

• Journal of Computing Science and Engineering
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• v.7 no.1
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• pp.53-66
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• 2013

Bounding the worst-case DRAM performance for a real-time application is a challenging problem that is critical for computing worst-case execution time (WCET), especially for multicore processors, where the DRAM memory is usually shared by all of the cores. Typically, DRAM commands from consecutive DRAM accesses can be pipelined on DRAM devices according to the spatial locality of the data fetched by them. By considering the effect of DRAM command pipelining, we propose a basic approach to bounding the worst-case DRAM performance. An enhanced approach is proposed to reduce the overestimation from the invalid DRAM access sequences by checking the timing order of the co-running applications on a dual-core processor. Compared with the conservative approach, which assumes that no DRAM command pipelining exists, our experimental results show that the basic approach can bound the WCET more tightly, by 15.73% on average. The experimental results also indicate that the enhanced approach can further improve the tightness of WCET by 4.23% on average as compared to the basic approach.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1704-1712
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• 2014

The unused Worst-Case Execution Time (WCET) allocated to a real-time task occurs when the actual execution time of the task can be far less than the WCET preassigned to the task for a schedulability test. Any unused WCET allocated to the task can be exploited to reduce the power consumption of battery-powered sensor nodes through real-time power-aware scheduling techniques. From the distribution perspective of the unused WCET, the unused WCET distribution policy is classified into three types: Conservative Unused WCET (CU-WCET), Moderate Unused WCET (MU-WCET), and Aggressive Unused WCET (AU-WCET) distribution policies. We evaluated the performance of real-time power-aware scheduling techniques incorporating each of three unused WCET distribution policies in terms of low power consumption.

• Journal of the Korea Society for Simulation
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• v.11 no.3
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• pp.23-34
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• 2002

Dynamic storage allocation (DSA) is a field fairly well studied for a long time as a basic problem of system software area. Due to memory fragmentation problem of DSA and its unpredictable worst case execution time, real-time system designers have believed that DSA may not be promising for real-time application service. Recently, the need for an efficient DSA algorithm is widely discussed and the algorithm is considered to be very important in the real-time system. This paper proposes an efficient DSA algorithm called QSB (quick semi-buddy) which is designed to be suitable for real-time environment. QSB scheme effectively maintains free lists based on quick-fit approach to quickly accommodate small and frequent memory requests, and the other free lists devised with adaptation upon a typical binary buddy mechanism for bigger requests in harmony for the .improved performance. Comprehensive simulation results show that the proposed scheme outperforms QHF which is known to be effective in terms of memory fragmentation up to about 16%. Furthermore, the memory allocation failure ratio is significantly decreased and the worst case execution time is predictable.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.4
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• pp.176-184
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• 2002

We provide a checkpointing framework reflecting both the timeliness and the dependability in order to make checkpointing applicable to dependable real-time systems. The predictability of real-time tasks with checkpointing is guaranteed by the worst case execution time (WCET) based on the allocated number of checkpoints and the permissible number of failures. The permissible number of failures is derived from fault tolerance requirements, thus guaranteeing the dependability of tasks. Using the WCET and the permissible number of failures of tasks, we develop an algorithm that determines the minimum number of checkpoints allocated to each task in order to guarantee the schedulability of a task set. Since the framework is based on the amount of time redundancy caused by checkpointing, it can be extended to other time redundancy techniques.

• Journal of the Korea Society of Computer and Information
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• v.11 no.6 s.44
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• pp.113-123
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• 2006

Flash memory has been increasingly used in handhold devices not only for data storage, but also for code storage. Because NAND flash memory only provides sequential access feature, a traditionally accepted solution to execute the program from NAND flash memory is shadowing. But, shadowing has significant drawbacks increasing a booting time of the system and consuming severe DRAM space. Demand paging has obtained significant attention for program execution from NAND flash memory. But. one of the issues is that there has been no effort to bound demand paging cost in flash memory and to analyze the worst case performance of demand paging. For the worst case timing analysis of programs running from NAND flash memory. the worst case demand paging costs should be estimated. In this paper, we propose two different WCRT analysis methods considering demand paging costs, DP-Pessimistic and DP-Accurate, depending on the accuracy and the complexity of analysis. Also, we compare the accuracy butween DP-Pessimistic and DP-Accurate by using the simulation.