• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.168-172
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• 1993

As the worst-case analysis for interval plants, a conjecture whether the supremum of the integral of square error(ISE) is attained at the extreme point such as vertices, Kharitonov vertices, CB segment, and edges is suggested. We present a sufficient condition for which the worst performance index occurs at one ofvertices of uncertain parameter space. Numerical examples are also given.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.148-159
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• 2005

We propose a technique for finding the worst case response time (WCRT) of a DMA request that is needed in the schedulability analysis of a whole real-time system. The technique consists of three steps. In the first step, we find the worst case bus usage pattern of each CPU task. Then in the second step, we combine the worst case bus usage pattern of CPU tasks to construct the worst case bus usage pattern of the CPU. This second step considers not only the bus requests made by CPU tasks individually but also those due to preemptions among the CPU tasks. finally, in the third step, we use the worst case bus usage pattern of the CPU to derive the WCRT of DMA requests assuming the fixed-priority bus arbitration protocol. Experimental results show that overestimation of the DMA response time by the proposed technique is within $20\%$ for most DMA request sizes and that the percentage overestimation decreases as the DMA request size increases.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2006.11a
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• pp.281-283
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• 2006

In this paper, we consider the problem of batch processing of orders, where either a single order or a pair of orders which satisfies specific conditions may be grouped in the same batch. The objective of the problem is to minimize the number of batches formed to accommodate all orders. We prose an approach based on a Known algorithm proven to be optimal for special class of problems with tree structure and show the approach to have the worst case ratio of $2-{\frac{2}{n}}$

• Journal of the Korean Operations Research and Management Science Society
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• v.15 no.2
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• pp.97-104
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• 1990

The problem is a variation of the weighted set-covering problem (SCP) which requires the minimum-cost cover to be self-covering. It is shown that direct extension of the well-known greedy heuristic for SCP can have an arbitrarily large error in the worst case. It remains an open question whther these exists a greedy heuristic with a finite error bound.

• Journal of the Korea Society of Computer and Information
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• v.11 no.6 s.44
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• pp.113-123
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• 2006

Flash memory has been increasingly used in handhold devices not only for data storage, but also for code storage. Because NAND flash memory only provides sequential access feature, a traditionally accepted solution to execute the program from NAND flash memory is shadowing. But, shadowing has significant drawbacks increasing a booting time of the system and consuming severe DRAM space. Demand paging has obtained significant attention for program execution from NAND flash memory. But. one of the issues is that there has been no effort to bound demand paging cost in flash memory and to analyze the worst case performance of demand paging. For the worst case timing analysis of programs running from NAND flash memory. the worst case demand paging costs should be estimated. In this paper, we propose two different WCRT analysis methods considering demand paging costs, DP-Pessimistic and DP-Accurate, depending on the accuracy and the complexity of analysis. Also, we compare the accuracy butween DP-Pessimistic and DP-Accurate by using the simulation.

• Journal of Internet Computing and Services
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• v.17 no.4
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• pp.51-60
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• 2016

Embedded software has requirements such as real-time and environment independency. The real-time requirement is affected from worst-case execution time of loaded tasks. Therefore, to guarantee real-time requirement, we need to determine a program's worst-case execution time using static analysis approach. However, the existing methods for worst-case execution time analysis do not consider the environment independency. Thus, in this paper, in order to provide environment independency, we propose a method for measuring task's execution time from the source codes. The proposed method measures the execution time through the control flow graph created from the source codes instead of the executable codes. However, the control flow graph created from the source code does not have information about execution time. Therefore, in order to provide this information, the proposed method identifies the relationships between statements in the source code and instructions in the executable code. By parameterizing those parts that are dependent on processors based on the relationships, it is possible to enhance the flexibility of the tool that measures the worst-case execution time.

• Journal of Computing Science and Engineering
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• v.4 no.2
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• pp.128-152
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• 2010

With the advance of computer and communication technologies, wireless sensor networks (WSNs) are increasingly used in many aspects of our daily life. However, since the battery lifetime of WSN nodes is restricted, the WSN lifetime is also limited. Therefore, it is crucial to determine this limited lifetime in advance for preventing service interruptions in critical applications. This paper proposes a feasible static analysis approach to estimating the worstcase lifetime of a WSN. Assuming known routes with a given sensor network topology and SMAC as the underlying MAC protocol, we statically estimate the lifetime of each sensor node with a fixed initial energy budget. These estimations are then compared with the results obtained through simulation which run with the same energy budget on each node. Experimental results of our research on TinyOS applications indicate that our approach can safely and accurately estimate worst-case lifetime of the WSN. To the best of our knowledge, our work is the first one to estimate the worst-case lifetime of WSNs through a static analysis method.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.56-59
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• 1996

Worst-case state estimation will be proposed in this paper. By using the worst-case disturbance and worst-case state estimation, we can obtain right/left constrained coprime factors. If constrained coprime factors are used in designing a controller, the infinity-norm of closed-loop transfer matrix can be smaller than any constant .gamma.(> .gamma.$_{opt}$) without matrix dilation optimization. The derivation of left/right constrained coprime factors is achieved by doubly coprime factorization for the plant constrained by the infinity norm. And the parameterization of stabilizing controllers gives us easily understanding for H$_{\infty}$ control theory.ry.

• Journal of Computing Science and Engineering
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• v.6 no.1
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• pp.12-25
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• 2012

For real-time systems it is important to obtain the accurate worst-case execution time (WCET). Furthermore, how to improve the WCET of applications that run on multicore processors is both significant and challenging as the WCET can be largely affected by the possible inter-core interferences in shared resources such as the shared L2 cache. In order to solve this problem, we propose an innovative approach that adopts a code positioning method to reduce the inter-core L2 cache interferences between the different real-time threads that adaptively run in a multi-core processor by using different strategies. The worst-case-oriented strategy is designed to decrease the worst-case WCET among these threads to as low as possible. The other two strategies aim at reducing the WCET of each thread to almost equal percentage or amount. Our experiments indicate that the proposed multicore-aware code positioning approaches, not only improve the worst-case performance of the real-time threads but also make good tradeoffs between efficiency and fairness for threads that run on multicore platforms.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.506-517
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• 2000

In distributed real-time system, a task activated by the completion of its preceding task can be modeled as a periodic task with activation jitter. An activation jitter of a task is defined asthe difference between the worst case and the best case response time of its preceding task. Becausethe existing approaches assume that the best case response time is much smaller than the actual one,the activation jitter and the worst case response time of lower priority tasks are overestimated. Thispaper proposes a new analysis technique to calculate the best case response time more precisely andto reduce the activation jitter bounds. The proposed technique obtains the best case response time byconsidering the relative phase between tasks. The precise analysis of the activation jitters can reducethe worst case response time of other tasks and increase the schedulability. The simulation resultsshow that the proposed analysis technique improves the accuracy of the best case and the worst caseresponse time up to 40% and 6%, respectively.