• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.133-141
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• 2020

The use of high-gain-voltage step-up converters for distributed power generation systems is being popularized because of the need for new energy generation and power conversion technologies. In this study, a new constructed high-gain-boost DC-DC converter was proposed to coordinate low voltage output DC sources, such as PV or fuel cell systems, with high DC bus (380 V) lines. Compared with traditional boost DC-DC converters, the proposed converter can create higher gain and has wider input voltage range and lower voltage stress for power semiconductors and passive elements. Moreover, the proposed topology produces multilevel DC voltage output, which is the main advantage of the proposed topology. Steady-state analysis in continuous conduction mode of the proposed converter is discussed in detail. The practicability of the proposed DC-DC converter is presented by experimental results with a 300 W prototype converter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.280-285
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• 2004

In this paper, a 9-bit analog-to-digital converter (ADC) is designed for optical disk drive (ODD) servo applications. In the ADC, the circuit technique to increase the operating range of the sample-and-hold amplifier is proposed, which can process the wide-varying input common-mode range. The algorithmic ADC structure is chosen so that the area can be significantly reduced, which is suitable for SoC integration. The ADC is fabricated in a 0.18-$\mu\textrm{m} $ CMOS 1P5M technology. Measurement results of the ADC show that SNDR is 51.5dB for the sampling rate of 6.5MS/s. The power dissipation is 36.3mW for a single supply voltage of 3.3V.

• Journal of Sensor Science and Technology
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• v.26 no.4
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• pp.223-227
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• 2017

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sensitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during integration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sensitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator determines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A $94{\times}150$ pixel array image sensor was designed using a conventional $0.18{\mu}m$ CMOS process and its performance was simulated.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.493-495
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• 2008

A new three-level resonant converter suitable for wide input variation is proposed. A hybrid combination of a three-level converter controlled by phase-shift modulation and a half-bridge converter is presented. Since the voltage of each switch is one half of the input voltage, it has advantages of the choice and characteristics of switches. The ZVS operation of the converter is achieved by using the magnetizing current of the transformer. To verify the theoretical analysis, experimental results of the proposed converter are presented.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.370-372
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• 2008

A resonant converter suitable for applications of wide input variation is proposed. A half-bridge converter and a phase-shift converter are combined in primary and the secondaries of each transformer are connected in series which makes four voltage levels. Furthermore, by adopting resonant converter scheme, a resonant capacitor is connected with the secondaries of the transformers in series and an output inductor is removed. Zero voltage switching is achieved from full load to no load. The analysis of the resonant converter and experimental results of 200W prototype is presented to verify the features of the converter.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1577-1583
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• 2015

In this research, a combined adaptive-robust current controller is developed for non-minimum-phase DC-DC converters in a wide range of operations. In the proposed nonlinear controller, load resistance, input voltage and zero interval of the inductor current are estimated using developed adaptation rules and knowing the operating mode of the converter for the closed-loop control is not required; hence, a single controller can be employed for a wide load and line changes in discontinuous and continuous conduction operations. Using the TMS320F2810 digital signal processor, the experimental response of the proposed controller is presented in different operating points of the buck/boost converter. During transition between different modes of the converter, the developed controller has a better dynamic response compared with previously reported adaptive nonlinear approach. Moreover, output voltage steady-state error is zero in different conditions.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.495-497
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• 2010

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.153-154
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• 2016

• Journal of Power Electronics
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• v.19 no.6
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• pp.1380-1392
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• 2019

Input filters are very important to matrix converters (MCs). They are used to improve grid side current waveform quality and to reduce the input voltage distortion supplied to the grid side. Due to the effects of the input filter and the output power, the grid side power factor (PF) is not at unity when the input power factor angle is zero. In this paper, the displacement angle between the grid side phase current and the phase voltage affected by the input filter parameters and output power is analyzed. Based on this, a new grid side PF unity compensation method implemented in the indirect space vector pulse width modulation (ISVPWM) method is presented, which has a larger compensation angle than the traditional compensation method, showing a higher grid side PF at unity in a wide output power range. Simulation and experimental results verify that the analysis of the displacement angle between the grid side phase current and the phase voltage affected by the input filter and output power is right and that the proposed compensation method has a better grid side PF at unity.