• Journal of the Korean Magnetics Society
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• v.24 no.4
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• pp.123-127
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• 2014

We developed a digital 3-axis flux-gate magnetometer for magnetic field signal measurement from warship during demagnetizing and degaussing processes. For the magnetometer design, we considered following points; the distance between magnetic field measurement station and magnetometer located under sea is about several 100 m, the magnetometer is exposed to magnetic field of ${\pm}1mT$ during demagnetizing process, and magnetometer is located under the sea about 30 m depth. To overcome long distance problem, magnetometer could be operated on wide input supply voltage range of 16~36 V using DC/DC converter, and for the data communication between the magnetometer and measurement station a RS422 serial interface was employed. To improve perming effect due to the ${\pm}1mT$ during demagnetizing process, magnetometer could be compensated external magnetic field up to ${\pm}1mT$ but magnetic field measuring rang is only ${\pm}100{\mu}T$. The perming effect was about ${\pm}2nT$ under ${\pm}1mT$ external magnetic field. The magnetometer was tested water vessel with air pressure up to 6 bar for the sea water pressure problems. Linearity of the magnetometer was better than 0.01 % in the measuring range of ${\pm}0.1mT$ and noise level was $30pT/\sqrt{Hz}$ at 1 Hz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.60-68
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• 2008

This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

• Journal of the Korean Society for Railway
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• v.20 no.3
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• pp.329-338
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• 2017

A recent trend of technical development in auxiliary-power-supplies (APS) is to replace 60Hz low frequency transformers with isolated type dc/dc converters. This paper introduces the technical trend in APS structures and proposes a power converter circuit suitable for high-efficient and light-weight APS. By utilizing the resonant converter, which achieves ZCS, to reduce switching losses, various types of APS structures (1-stage and 2-stage) are reviewed, and they are verified by simulation. The full-bridge resonant LLC converter is designed with a 1-stage power converting structure; the resonant converter topology is designed with a 2-stage power converting structure that has a pre-regulator converter to compensate for the wide input voltage range. Both a step-down converter and a step-up converter are designed and compared for the pre-regulator in the 2-stage structure. Operational characteristics are compared with simulation results and loss analyses are presented to proposes appropriate system structure and topologies.