• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.418.2-418.2
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• 2016

$Al_2O_3$ passivation layer has excellent passivation properties at p-type Si surface. This $Al_2O_3$ layer forms thin $SiO_2$ layer at the interface. There were some studies about inserting thermal oxidation process to replace naturally grown oxide during $Al_2O_3$ deposition. They showed improving passivation properties. However, thermal oxidation process has disadvantage of expensive equipment and difficult control of thin layer formation. Wet chemical oxidation has advantages of low cost and easy thin oxide formation. In this study, $Al_2O_3$/$SiO_2/Si(100)$ interface was formed by wet chemical oxidation and PA-ALD process. $SiO_2$ layer at Si wafer was formed by $HCl/H_2O_2$, $H_2SO_4/H_2O_2$ and $HNO_3$, respectively. 20nm $Al_2O_3$ layer on $SiO_2/Si$ was deposited by PA-ALD. This $Al_2O_3/SiO_2/Si(100)$ interface were characterized by capacitance-voltage characteristics and quasi-steady-state photoconductance decay method.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.340-340
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• 2012

최근 MOS 소자들이 게이트 산화막을 Mono-layer가 아닌 Multi-Layer을 사용하는 추세이다. Bulk와 High-k물질간의 Dangling Bond를 줄이기 위해 Passivation 층을 만드는 것을 예로 들 수 있다. 이러한 Double Layer의 쓰임이 많아지면서 계면에서의 Interface State Density의 영향도 커지게 되면서 이를 측정하는 방법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 $SiO_2$ Double Layer의 Interface State Density를 Conductance Method를 사용하여 구하는 연구를 진행하였다. Wet Oxidation과 Chemical Vapor Deposition (CVD) 공정을 이용하여 $SiO_2$ Double-layer로 증착한 후 Aluminium을 전극으로 하는 MOS-Cap 구조를 만들었다. 마지막 공정은 $450^{\circ}C$에서 30분 동안 Forming-Gas Annealing (FGA) 공정을 진행하였다. LCR meter를 이용하여 high frequency C-V를 측정한 후 North Carolina State University California Virtual Campus (NCSU CVC) 프로그램을 이용하여 Flatband Voltage를 구한 후에 Conductance Method를 측정하여 Dit를 측정하였다. 본 연구 결과 Double layer (Wet/CVD $SiO_2$)에 대해서 Conductance Method를 방법을 이용하여 Dit를 측정하는 것이 유효하다는 것을 확인 할 수 있었다. 본 실험은 앞으로 많이 쓰이고 측정될 Double layer (Wet/CVD $SiO_2$)에 대한 Interface State Density의 측정과 분석에 대한 방향을 제시하는데 도움이 될 것이라 판단된다.

• Journal of the Korean Ceramic Society
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• v.52 no.6
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• pp.455-461
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• 2015

Porous ceramics with tailored pore size and shape are promising materials for the realization of a number of functional and structural properties. A novel method has been reported for the investigation of the role of SiC in the formation of $SiO_2$ foams by colloidal wet processing. Within a suitable pH range of 9.9 ~ 10.5 $SiO_2$, particles were partially hydrophobized using hexylamine as an amphiphile. Different mole ratios of the SiC solution were added to the surface modified $SiO_2$ suspension. The contact angle was found to be around $73^{\circ}$, with an adsorption free energy $6.8{\times}10^{-12}J$. The Laplace pressure of about 1.25 ~ 1.6 mPa was found to correspond to a wet foam stability of about 80 ~ 85%. The mechanical and thermal properties were analyzed for the sintered ceramics, with the highest compressive load observed at the mole ratio of 1:1.75. Hertzian indentations are used to evaluate the damage behavior under constrained loading conditions of $SiO_2$-SiC porous ceramics.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.104-104
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• 2000

MOS소자의 크기가 작아짐에 따라 gate 유전막의 두께 또한 얇아져야 한다. 두께가 얇아짐에 따라 gate 유전막으로써 기존의 SiO2는 direct tunneling으로 인해 높은 누설전류를 수반한다. 그래서 높은 유전상술르 가지는 물질들에 대한 연구의 필요성이 대두되고 있다. 그중 CVD-Ta2O5는 차세대 MOSFET소자기술에 있어서 높은 유전상수($\varepsilon$r+25)와 우수한 step coverage 때문에 각광을 받고 있는 물질중에 하나이다. 본 연구에서는 Ta2O5를 gate를 유전막으로 사용하고 RTN처리와 wet oxidation을 접목시켜 이들의 전기적인 특성을 향상시킬 수 있었다. p-형 wafer 위에 D2와 O2를 사용하여 SiO2(100 )를, NH3를 이용하여 Nitridation(10 )을 전처리로써 각각 실시하였고 그 위에 MOCVD방법으로 Ta2O5를 80 성장시켰다. 첫 번째 시편은 45$0^{\circ}C$ 10min동안 wet oxidation을 시켰고, 두 번째 시편은 $700^{\circ}C$ 60sec동안 NH3 분위기에서 RTN 처리를 하였다. 세 번째 시편은 동일조건으로 RTN 처리후 wet oxidation을 하였다. 그 후 각각의 시편을 capacitor를 제작하고 그 전기적 특성을 관찰하였다. Wet oxidation만을 시킨 시편은 as-deposited Ta2O5 시편에 비해서 -1.5V에서 누설전류는 약 2~3 order정도 감소되었고 accumulation 영역에서의 capacitance 값은 oxide층의 성장(5 )을 무시하면 거의 변화하지 않았다. RTN처리만 된 시편의 경우는 -1.5V에서 누설전류는 2~3order 정도 증가되었지만, accumulation 영역에서 capacitance 값은 거의 2qwork 증가하였다. 이 두가지 공정을 접목시킨 즉 RTN 처리후 wet oxidation 처리된 시편의 경우는 as-deposited Ta2O5 시편에 비해서 -1.5V에서 누설전류는 1 order 정도 감소하였고, accumulation 지역에서의 capacitance 값은 약 2배 증가하였다. 즉 as deposited Ta2O5 시편의 accumulation 지역의 capacitance 값은 12.8 fF/um2으로써 그 유효두께는 27.0 이었지만, RTN 처리후에 wet oxidation 시킨 시편의 accumulation 지역의 capacitance값은 21.2fF/um2으로써 그 유효두께는 16.3 이 되었다. 결론적으로 as deposited Ta2O5 시편에 RTN 처리후 wet oxidation을 실시한 결과 capacitance 값이 약 2배정도 증가하였고 누설전류는 약 1 order 정도 감소됨을 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.111-117
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• 2008

We have studied surface roughness, contamination of impurity, bonding with some gas element, reflectance and zeta potential on masks to be generated or changed during photolithography/dry or wet etching process. Mask surface roughness was not changed after photolithography/dry etching process. But surface roughness was changed on some area under MoSi film of Cr/MoSi/Qz. There was not detected any impurity on mask surface after plasma dry etching process. Reflectance of mask was increased after variable plasma etching treatment, especially when mask was treated with plasma including $O_2$ gas. Blank mask was positively charged when the mask was treated with Cr plasma etching gas($Cl_2:250$ sccm/He:20 $sccm/O_2:29$ seem, source power:100 W/bias power:20 W, 300 sec). But this positive charge was changed to negative charge when the mask was treated with $CF_4$ gas for MoSi plasma etching, resulting better wet cleaning. There was appeared with negative charge on MoSi/Qz mask treated with Cr plasma etching process condition, and this mask was measured with more negative after SC-1 wet cleaning process, resulting better wet cleaning. This mask was charged with positive after treatment with $O_2$ plasma again, resulting bad wet cleaning condition.

• Bulletin of the Korean Chemical Society
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• v.31 no.10
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• pp.2961-2966
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• 2010

Reduction of carbonyl compounds such as aldehydes, ketones, $\alpha,\beta$-unsaturated enals and enones, $\alpha$-diketones and acyloins was carried out readily with $NaBH_3CN$ in the presence of wet $SiO_2$ as a neutral media. The reactions were performed at solvent-free conditions in oil bath (70 - $80^{\circ}C$) or under microwave irradiation (240 W) to give the product alcohols in high to excellent yields. Regioselective 1,2-reduction of conjugated carbonyl compounds took place in a perfect selectivity without any side product formation.

• Bulletin of the Korean Chemical Society
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• v.24 no.7
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• pp.1021-1022
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• 2003

• Journal of the Korean Ceramic Society
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• v.34 no.3
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• pp.314-322
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• 1997

The thin film processing and the applicability as a IMD material of SiO2 aerogels providing ultralow dielec-tric properties were studied. The SiO2 aerogel films with 0.5g/㎤ density (78% porosity) and 4000~21000$\AA$ thickness could be prepared at 25$0^{\circ}C$ and 1160 psig by supercritical drying of wet-gel films, which were spin-coated at the spin rate of 1000~7000 rpm on p-Si(111) wafer under the isopropanol atmosphere. The optimum viscosity of polymeric SiO2 sols for spin coating was in the range of 10~14 cP. The main fac-tors being able to control the film thickness and microstructures were found to be sol concentration, spin rpm, and aging time of wet-gel films. The dielectric constant of the SiO2 aerogel thin film was around 2.0 low enough to be applied to the next generation semiconductor device beyond the giga level.

• Korean Journal of Materials Research
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• v.11 no.2
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• pp.71-75
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• 2001

The reaction stability of nickel with side-wall materials of SiO$_2$ and Si$_3$N$_4$ on p-type 4"(100) Si substrate were investigated. Ni on 1300 $\AA$ thick SiO$_2$ and 500 $\AA$ - thick Si$_3$N$_4$ were deposited. Then the samples were annealed at 400, 500, 750 and 100$0^{\circ}C$ for 30min, and the residual Ni layer was removed by a wet process. The interface reaction stability was probed by AES depth Profiling. No reaction was observed at the Ni/SiO$_2$ and Ni/Si$_3$N$_4$, interfaces at 400 and 50$0^{\circ}C$. At 75$0^{\circ}C$, no reaction occurred at Ni/SiO$_2$ interface, while $NiO_x$ and Si$_3$N$_4$ interdiffused at Ni/Si$_3$N$_4$ interface. At 100$0^{\circ}C$, Ni layers on SiO$_2$ and Si$_3$N$_4$ oxidized into $NiO_x$ and then $NiO_x$ interacted with side-wall materials. Once $NiO_x$ was formed, it was not removed in wet etching process and easily diffused into sidewall materials, which could lead to bridge effect of gate-source/drain.

• Electrical & Electronic Materials
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• v.8 no.1
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• pp.71-76
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• 1995

The thermal oxidation of Ge$_{0.2}$Si$_{0.8}$ in wet ambient has been investigated by Rutherford Backscattering Spectrometry(RBS). A uniform Ge$_{0.2}$Si$_{0.8}$O$_{2}$ oxide is formed at temperatures below 650.deg. C for polycrystalline and below 700.deg. C for single crystalline substrates. At higher temperatures Ge becomes depleted from the oxide and finally SiO$_{2}$ oxide is formed with Ge piled-ub behind it. The transition between the different oxide types depends also on the crystallinity of Ge$_{0.2}$Si$_{0.8}$. When a uniform Ge$_{0.2}$Si$_{0}$8/O$_{2}$ oxide grows, its thickness is proportional to the square root of the oxidation time, which suggests that the rate noting process is the diffusive transport of oxidant across the oxide. It is believed the oxidation is controlled by the competition between the diffusion of Ge or Si in Ge$_{0.2}$Si$_{0.8}$ and the movement of oxidation front.t.oxidation front.t.