• Title/Summary/Keyword: Weighted voltage mode control

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Multiple Output Forward Converter for PC Power Supply with Weighted Voltage Mode Control (가중치 전압 모드 제어를 적용한 PC 전원용 다중출력 포워드 컨버터)

  • 이경주;김성민;이득기;정종진;김흥근
    • The Transactions of the Korean Institute of Power Electronics
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    • v.6 no.4
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    • pp.307-316
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    • 2001
  • In this paper, the multiple output forward converter forPC power supply with weighted voltage mode control which improves the characteristics of DC and transient responses is analyzed and designed. The power stage model of this converter including all the major parasitic components is derived and the small signal model is also derived. Determination of the weighting factors and a design procedure for the loop compensation are presented. Finally, the proposed controller is verified through the simulation of three output forward converter with SABER, and the experiment.

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Weighted Voltage Mode Control of Multiple Output Forward Converter for PC Power Supply (PC 전원용 다중출력 포워드 컨버터의 가중치 전압 모드 제어)

  • 차영길
    • Proceedings of the KIPE Conference
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    • 2000.07a
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    • pp.501-504
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    • 2000
  • In this paper the PC power supply is studied from the point of system stability. The power stage model of a multiple output forward converter with weighted voltage mode control is derived including all the major parasitic components and the small signal model is also derived. Determination of the weighting factors and a design procedure for the loop compensation are presented. Finally the model is verified through the simulation of three output forward converter with SABER.

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A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level

  • Bae, Chang-Hyun;Choi, Dong-Ho;Ahn, Keun-Seon;Yoo, Changsik
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.5
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    • pp.423-429
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    • 2013
  • A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

A Study on the Design of D/A Converter based on Data Weighted Average Technique for enhancement of reliability (혼합형 전류 구동 D/A 컨버터 설계 제작에 있어서 데이터 가중평균기법을)

  • Kim, S.D.;Woo, Y.S.;Kim, D.G.;Sung, M.Y.
    • Proceedings of the KIEE Conference
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    • 1999.07g
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    • pp.3215-3217
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    • 1999
  • In this paper, a new structure of realizing switching control logic for Data Weighted Average Technique is suggested. It uses memory and adder for summing past binary input and this summed data is used to select one switch in control logic. This control logic acts in parallel regardless of resolution so increasing resolution don't affect on converting speed. In this reason, high speed and high resolution D/A converter based on Data Weighted Average Technique could be made. In this paper, 4 bits current mode thermometer code D/A converter is degined and simulated by using HSPICE. Simulated results show that new structure of D/A converter has more than 250MHz converting speed and less than 0.0003[LSB] INL error. It is very useful in low power circuit because of using 3.3 V supply voltage.

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Fast-Transient Digital LDO Regulator With Binary-Weighted Current Control (이진 가중치 전류 제어 기법을 이용한 고속 응답 디지털 LDO 레귤레이터)

  • Woo, Ki-Chan;Sim, Jae-Hyeon;Kim, Tae-Woo;Hwang, Seon-Kwang;Yang, Byung-Do
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.6
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    • pp.1154-1162
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    • 2016
  • This paper proposes a fast-transient digital LDO(Low dropout) regulator with binary-weighted current control technique. Conventional digital LDO takes a long time to stabilize the output voltage, because it controls the amount of current step by step, thus ringing problem is generated. Binary-weighted current control technique rapidly stabilizes output voltage by removing the ringing problem. When output voltage reliably reaches the target voltage, It added the FRZ mode(Freeze) to stop the operation of digital LDO. The proposed fast response digital LDO is used with a slow response DC-DC converter in the system which rapidly changes output voltage. The proposed digital controller circuit area was reduced by 56% compared to conventional bidirectional shift register, and the ripple voltage was reduced by 87%. A chip was implemented with a $0.18{\mu}F$ CMOS process. The settling time is $3.1{\mu}F$ and the voltage ripple is 6.2mV when $1{\mu}F$ output capacitor is used.