• Journal of Broadcast Engineering
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• v.6 no.1
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• pp.32-40
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• 2001

In this paper, we propose a DWT (discrete Wavelet Transform) based watermarking method, which can be conveniently Integrated In the up-coming JPEG2770 baseline system. Although Conventional DWT based watermarking techniques insert watermark signal Into wavelet coefficients after the transform, our proposed method embeds a watermark into wavelet coefficients obtained from the ongoing process of lifting for DWT. The proposed method allows us to selectively determine frequency characteristics of the coefficients where the watermark is embedded. so that the Inserted watermark cannot be removed or altered even when the filter-bank for DWT is known. Through the simulation, we show that the proposed method is more secure and more robust against various attacks than conventional DWT barred watermarking techniques.

• Journal of Korea Multimedia Society
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• v.8 no.1
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• pp.19-26
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• 2005

The basis function of wavelet transform used in this paper is constructed by using lifting scheme, which is different from general wavelet transform. Lifting scheme is a new biorthogonal wavelet con-structing method, that does not use Fourier transform for constructing its basis function. In this paper, an image compression and reconstruction method using the lifting scheme was proposed. And this method improves data visualization by supporting a partial reconstruction and a local reconstruction. Approx- imations at various resolutions allow extracting various sizes of feature from an image or signal with a small amount of original information. An approximation with small size of scaling coefficients gives a brief outline of features at fast. Image compression and edge detection techniques provide good frame- works for data management and visualization in multimedia database.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2315-2318
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• 2003

The Wavelet Transform has been applied in mathematics and computer sciences. Numerous studies have proven its advantages in image processing and data compression, and have made it a basic encoding technique in data compression standards like JPEG2000 and MPEG-4. Software implementations of the Discrete Wavelet Transform (DWT) appears to be the performance bottleneck in real-time systems in terms of performance. And hardware implementations are not flexible. Therefore, FPGA implementations of the DWT has been a topic of recent research. The goal of this thesis is to investigate of FPGA implementations of the DWT Processor for image compression applications. The DWT processor design is based on the Lifting Based Wavelet Transform Scheme, which is a fast implementation of the DWT The design uses various techniques. The DWT Processor was simulated and implemented in a FLEX FPGA platform of Altera

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.515-518
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• 2000

디지털 워터마킹(Digital Watermarking)은 디지털 미디어 창작물에 대해 불법적인 사용과 인위적인 조작으로부터 소유권과 저작권을 보호하기 위하여 입증 가능한 정보(워터마크)를 사람이 인지하지 못하도록 삽입하는 기술이다. 본 논문에서는 JPEG 2000에서 지원하는 Daubechies 9/7 필터를 이용한 lifting 기반의 DWT(Discrete Wavelet Transform) 중간에 임의의 파라메터를 추가한 lifting 단계를 구성하여 이 부분에 워터마크를 삽입한 후, 다양한 신호처리 왜곡을 가하여 제안한 방법의 성능을 평가하였다. 실험은 8-bit 512×512크기의 영상을 사용하였으며, 무작위로 발생시킨 1과-1을 워터마크 신호로 하여 DWT 시 추가한 lifting 단계에서의 임의의 파라메터 값과 워터마크를 삽입할 각 웨이블릿 변환의 해상도 레벨을 조절해 가면서 선택한 웨이블릿 계수값에 무작위로 발생시킨 워터마크 신호를 삽입하였다. 실험 결과 영상의 일반적인 변형(압축, 필터링 등)에 대해서 제안한 방법의 워터마킹 기법의 성능이 전반적으로 강인함을 확인하였다.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.173-179
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• 2012

In this paper, we propose an efficient architecture for 2D IWT using an existing 1D IWT. Lifting based IWT is the architecture of which a multiplier is replaced by adders and shift registers. The structure is relatively simple and modular. The proposed architecture to process an image size with 256x256 pixels consists of 16 adders, 8 shift registers, and some memories. By processing two rows at the same time, 2D sub-band coefficients can be calculated immediately after 1D sub-band coefficients have been processed. The architecture is designed so that each image can be inputted consecutively. The number of adders and shift registers is increased by twice comparing the existing architecture, but the memory size and the execution time are decreased by half. The proposed architecture is implemented using Verilog-HDL and simulated using iSim. It is synthesized and demonstrated at ISE for xc5vlx330 in RPS3K board.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.282-285
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• 2000

Three representations are known to implement the discrete wavelet transform (DWT) ; i.e., direct, lifting and matrix forms. In these representations, direct and lifting forms are well known so far. This paper derives the matrix form of the DWT from the direct form. Then, we implement these three representations on a programmable digital signal processor (in the following, DSP processor) and compare them in terms of the number of calculations and instruction cycles. As a result, we confirm that the lifting form has the lowest number of calculations and cycles, and the matrix form has an effective decrease in the number of cycles than other representations on the DSP processor.

• Proceedings of the KAIS Fall Conference
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• 2008.11a
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• pp.236-239
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• 2008

무선 센서 네트워크에서 센서 노드는 그 목적에 따라 다양한 신호처리 기능을 가져야 한다. 센서 노드의 에너지 제약과 통신 대역폭 제한은 센서 노드에서의 가벼운 신호처리 기법을 필요로 한다. 일반적인 센서 노드에서의 신호처리 기법은 센서 노드에 수신된 신호를 잡음제거 등의 전처리를 수행하고, 에너지를 계산하여 표적의 위치를 탐지하고 기지국에서의 위치추정 및 식별을 위하여 특징 추출하거나 압축하여 전송하는 등의 방법으로 구성된다. 이러한 센서 노드에서 필수적인 신호처리 기법들은 에너지 효율적인 신호처리 기법은 무선 센서 네트워크의 생존 시간과 표적 탐지 및 식별이라는 목적에 대한 성능에 큰 영향을 끼치게 된다. 본 논문에서는 무선 센서 네트워크에서 센서 노드의 필수적인 신호처리를 Lifting scheme wavelet 방법을 이용하여 센서 노드에서 에너지 효율적인 신호처리 기법을 제안한다.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.864-867
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• 2005

In this paper we introduce a design of parallel architecture for wavelet transformation on FPGA. We implement wavelet transforms though lifting scheme and apply Daubechies4 transform equations. This technique has an advantage that we can obtain perfect reconstruction of the data. We divide our process to high pass filter and low pass filter. With this division, we can find coefficients from low and high pass filters simultaneously using parallel processing properties of FPGA to reduce processing time. From the equations, we have to design real number computation module, referred to IEEE754 standard. We choose 32 bit computation that is fine enough to reconstruct data. After that we arrange the real number module according to Daubechies4 transform though lifting scheme.

• Proceedings of the KSRS Conference
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• 2004.10a
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• pp.224-227
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• 2004

From 1980's, the DWT(Discrete Wavelet Transform) is applied to the data/image processing. Many people use the DWT in remote sensing for diversity purposes and they are satisfied with the wavelet theory. Though the algorithm for wavelet is very diverse, many people use the standard wavelet such as Daubechies D4 wavelet and biorthogonal 9/7 wavelet. We will overview the wavelet theory for discrete form which can be applied to the image processing. First, we will introduce the basic DWT algorithm and review the wavelet algorithm: EZW (Embedded Zerotree Wavelet), SPIHT(Set Partitioning in Hierarchical Trees), Lifting scheme, Curvelet, etc. Finally, we will suggest the properties of wavelet algorithm; and wavelet filter for each image processing in remote sensing.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.883-886
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• 2003

본 논문에서는 Lifting-Based Scheme을 이용한 DWT(Discrete Wavelet Transform) 의 개선된 행 처리기의 구조를 제안 하였다. 제안된 행 처리기는 3개의 Adder 와 2개의 shifter를 사용 하였고 dual-port RAM을 사용하여 파이프 라인 구조를 취하여 각 클럭마다 열처리기에서 사용할 데이터를 발생 한다. 이러한 행 처리기의 파이프 라인 구조를 개선하여 Adder를 줄이고 행 처리기의 이용률을 최대로 하여 하드웨어의 공간적 비용 절감 효과를 가져 왔다. 제안된 구조는 Verilog를 사용하여 RTL설계를 한뒤 시뮬레이션으로 그 동작을 확인 하였다.