• Journal of the Microelectronics and Packaging Society
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• v.29 no.1
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• pp.49-54
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• 2022

The copper plating process used to fabricate the submicron damascene pattern of Cu wiring for Si wafer was applied to the plating of a PCB pattern of several tens of microns in size using the same organic additives and current density conditions. In this case, the non-uniformity of the plating thickness inside the pattern was observed. In order to quantitatively analyze the cause, a numerical calculation considering the solution flow and electric field was carried out. The calculation confirmed that the depletion of Cu²⁺ ions in the solution occurred relatively earlier at the bottom corner than the upper part of the pattern due to the plating of the sidewall and the bottom at the corner of the pattern bottom. The diffusion coefficient of Cu²⁺ ions is 2.65 10^-10 m²/s, which means that Cu²⁺ ions move at 16.3 ㎛ per second on average. In the cases of small damascene patterns, the velocity of Cu²⁺ ions is high enough to supply sufficient ions to the inside of the patterns, while sufficient time is required to replenish the exhausted copper ions in the case of a PCB pattern having a size of several tens of microns. Therefore, it is found that the thickness uniformity can be improved by reducing the current density to supply sufficient copper ions to the target area.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.193-193
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• 2012

In thin film silicon solar cells, p-i-n structure is adopted instead of p/n junction structure as in wafer-based Si solar cells. PECVD is the most widely used thin film deposition process for a-Si:H or ${\mu}c$-Si:H solar cells. Single-chamber PECVD system for a-Si:H solar cell manufacturing has the advantage of lower initial investment and maintenance cost for the equipment. However, in single-chamber PECVD system, doped and intrinsic layers are deposited in one plasma chamber, which inevitably impedes sharp dopant profiles at the interfaces due to the contamination from previous deposition process. The cross-contamination between layers is a serious drawback of single-chamber PECVD system. In this study, a new plasma process to solve the cross-contamination problem in a single-chamber PECVD system was suggested. In order to remove the deposited B inside of the plasma chamber during p-layer deposition, a high RF power was applied right after p-layer deposition with SiH4 gas off, which is then followed by i-layer, n-layer, and Ag top-electrode deposition without vacuum break. In addition to the p-i interface control, various interface control techniques such as FTO-glass pre-annealing in O2 environment to further reduce sheet resistance of FTO-glass, thin layer of TiO2 deposition to prevent H2 plasma reduction of FTO layer, and hydrogen plasma treatment prior to n-layer deposition, etc. were developed. The best initial solar cell efficiency using single-chamber PECVD system of 10.5% for test cell area of 0.2 $cm^2$ could be achieved by adopting various interface control methods.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.313-313
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• 2012

In recent years there have been many studies of InGaN/GaN based light emitting diodes (LEDs) in order to progress the performance of luminescence. Many previous literatures showed the performance of LEDs by changing the LED structures and substrates. However, the studies carried out by the researchers so far were very complicated and sometimes difficult to apply in practice. Therefore, we propose one simple method of changing the thickness and the numbers of multiple quantum wells (MQWs) in order to optimize their effects. In our research, we investigated electrical and optical properties by changing the well thickness and the number of quantum well (QW) pair in LED structures by growing the structure -inch Si (111) wafer. We defined the samples from LED_1 to LED_3 according to MQW structure. Samples LED_1, LED_2 and LED_3 consist of 5-pair InGaN/GaN (3.5 nm/ 4.5 nm), 5-pair InGaN/GaN (3 nm/4.5 nm) and 7-pair InGaN/GaN (3.5 nm/4.5 nm), respectively. We characterized electrical and optical properties by using electroluminescence (EL) measurement. Also, Efficiency droop was analyzed by calculating external quantum efficiency (EQE) with varying injection current. The EL spectra of three samples show different emission wavelength peaks, FWHM and the blueshift of wavelength caused by screening the internal electric field because of the effect of different MQW structure. The results of optical properties show that the LED_2 sample reduce the internal electric field in QW than LED_1 from EL spectra. the increase in the number of QW pairs reduces the strain and increase the In composition in MQW. And, the points of efficiency droop's peak show different trend from LED_1 to LED_3. It is related with the carrier density in active region. Thus, from the results of experiments, we are able to achieve high performance LEDs and a reduction of efficiency droop and emission wavelength blueshift by optimizing MQWs structure.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.406-406
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• 2016

To get high efficiency n-type crystalline silicon solar cells, passivation is one of the key factor. Tunnel oxide (SiO2) reduce surface recombination as a passivation layer and it does not constrict the majority carrier flow. In this work, the passivation quality enhanced by different chemical solution such as HNO3, H2SO4:H2O2 and DI-water to make thin tunnel oxide layer on n-type crystalline silicon wafer and changes of characteristics by subsequent annealing process and firing process after phosphorus doped amorphous silicon (a-Si:H) deposition. The tunneling of carrier through oxide layer is checked through I-V measurement when the voltage is from -1 V to 1 V and interface state density also be calculated about $1{\times}1012cm-2eV-1$ using MIS (Metal-Insulator-Semiconductor) structure . Tunnel oxide produced by 68 wt% HNO3 for 5 min on $100^{\circ}C$, H2SO4:H2O2 for 5 min on $100^{\circ}C$ and DI-water for 60 min on $95^{\circ}C$. The oxide layer is measured thickness about 1.4~2.2 nm by spectral ellipsometry (SE) and properties as passivation layer by QSSPC (Quasi-Steady-state Photo Conductance). Tunnel oxide layer is capped with phosphorus doped amorphous silicon on both sides and additional annealing process improve lifetime from $3.25{\mu}s$ to $397{\mu}s$ and implied Voc from 544 mV to 690 mV after P-doped a-Si deposition, respectively. It will be expected that amorphous silicon is changed to poly silicon phase. Furthermore, lifetime and implied Voc were recovered by forming gas annealing (FGA) after firing process from $192{\mu}s$ to $786{\mu}s$. It is shown that the tunnel oxide layer is thermally stable.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.65-74
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• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

• Korean Chemical Engineering Research
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• v.44 no.5
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• pp.513-519
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• 2006

We developed two kinds of the microchip for application to electrophoresis based on both glass and quartz employing the MEMS fabrications. The poly-Si layer deposited onto the bonding interface apart from channel regions can play a role as the optical slit cutting off the stray light in order to concentrate the UV ray, from which it is possible to improve the signal-to-noise (S/N) ratio of the detection on a chip. In the glass chip, the deposited poly-Si layer had an important function of the etch mask and provided the bonding surface properly enabling the anodic bonding. The glass wafer including more impurities than quartz one results in the higher surface roughness of the channel wall, which affects subsequently on the microflow behavior of the sample solutions. In order to solve this problem, we prepared here the mixed etchant consisting HF and $NH_4F$ solutions, by which the surface roughness was reduced. Both the shape and the dimension of each channel were observed, and the electroosmotic flow velocities were measured as 0.5 mm/s for quartz and 0.36 mm/s for glass channel by implementing the microchip electrophoresis. Applying the optical slit with poly-Si layer provides that the S/N ratio of the peak is increased as ca. 2 times for quartz chip and ca. 3 times for glass chip. The maximum UV absorbance is also enhanced with ca. 1.6 and 1.7 times, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.145-145
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• 2008

High-k materials have been paid much more attention for their characteristics with high permittivity to reduce the leakage current through the scaled gate oxide. Among the high-k materials, $ZrO_2$ is one of the most attractive ones combing such favorable properties as a high dielectric constant (k= 20 ~ 25), wide band gap (5 ~ 7 eV) as well as a close thermal expansion coefficient with Si that results in good thermal stability of the $ZrO_2$/Si structure. During the etching process, plasma etching has been widely used to define fine-line patterns, selectively remove materials over topography, planarize surfaces, and trip photoresist. About the high-k materials etching, the relation between the etch characteristics of high-k dielectric materials and plasma properties is required to be studied more to match standard processing procedure with low damaged removal process. Among several etching techniques, we chose the inductively coupled plasma (ICP) for high-density plasma, easy control of ion energy and flux, low ownership and simple structure. And the $BCl_3$ was included in the gas due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. During the etching process, the wafer surface temperature is an important parameter, until now, there is less study on temperature parameter. In this study, the etch mechanism of $ZrO_2$ thin film was investigated in function of $Cl_2$ addition to $BCl_3$/Ar gas mixture ratio, RF power and DC-bias power based on substrate temperature increased from $10^{\circ}C$ to $80^{\circ}C$. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by scanning emission spectroscope (SEM). The chemical state of film was investigated using energy dispersive X-ray (EDX).

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.183-190
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• 2013

In this paper, we propose an improved anisotropic diffusion model for micro-crack detection in heterogeneously textured surface of polycrystalline solar wafers. Due to the nature of the image sensor, the gray-level of the diagonal micro-crack is non-uniform. Thus, the conventional algorithms can't fully detect diagonal micro-cracks when the number of iteration is not enough. However, the increasing of the iteration number leads to increase computation time and detects micro-crack thicker than the original micro-crack. In order to overcome this drawback, we use the gradient of north, south, east, and west directions as well as extended directions. To calculate the diffusion coefficients, we compare the gradients of conventional directions and extended directions and apply the larger gradient values to the coefficient function. This is because the proposed method reflects the information of diagonal micro-crack. Comparing to Tsai et al.'s and Ko and Rheem's, the proposed algorithm shows superior efficiency in detecting the diagonal micro-cracks with less iterations in the images of polycrystalline solar wafers. In addition, it also shows that the thickness of segmented micro-crack is similar to the orignal micro-crack.

• Journal of Korean Ophthalmic Optics Society
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• v.14 no.1
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• pp.57-62
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• 2009

Purpose: TiN films were deposited on sus304 by unbalanced magnetron sputtering system which was designed and developed as unbalancing the strength of the magnets in the magnetron electrode. The color and hardness of deposited TiN films was investigated. Methods: The cross sections of deposited films on silicon wafer were observed by SEM to measure the thickness of the films, the components of the surface of the films were identified by XPS, the components of the inner parts of the films were observed by XPS depth profiling. XPS high resolution scans and curve fittings of deposited films were performed for quantitative chemical analysis, Vickers micro hardness measurements of deposited films were performed with a nano indenter equipment. Results: The colors of deposited films gradually changed from light gold to dark gold, light violet, and indigo color with increasing of the thickness. It could be seen that the color change come from the composite change of three compound,$TiO_{x}N_{y}$, $TiO_2$, TiN. Especially, the composite change of$TiO_{x}N_{y}$ compound was thought to affect the color change with respect to thickness. Conclusions: Deposited films had lower than the value of general TiN film in Vickers hardness, which was caused by mixing three TiN, $TiO_2$,$TiO_{x}N_{y}$ compound in the deposited films. The increasing and decreasing of micro hardness with respect to thickness was thought to have something to do with the composite of TiN in the films.