• 마이크로전자및패키징학회지
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• 제18권1호
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• pp.15-21
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• 2011

전자기기의 고집적화를 위해 실리콘 웨이퍼의 두께가 점점 얇아지고 있으며 이로 인해 제조공정 중 균열이나 파손이 발생할 가능성이 높아지고 있다. 본 연구에서는 300 ${\mu}m$~100 ${\mu}m$ 두께의 반도체용 단결정 실리콘 웨이퍼의 파단 강도 및 파괴특성을 평가하였다. 기계적 연마를 통해 두께 (300, 200, 180, 160, 150, 100 ${\mu}m$)가 다른 실리콘 웨이퍼를 준비하였다. 하나의 웨이퍼에서 40개의 실리콘 다이(크기 : 62.5 mm${\times}$4 mm)를 얻어 4점 굽힘시험을 통해 평균 강도값을 구하였다. 강도분포의 통계적 해석을 위해 와이블 선도를 이용하여 형상인자(와이블 계수)와 크기인자(확률적 파괴강도)를 얻었다. 취성 실리콘 다이의 시편 크기(두께)효과와 파단 확률이 고려된 통계적 파단강도 값을 실리콘 다이 두께의 함수로 얻었다. 관찰된 파괴양상을 측정된 파단강도와 관련하여 고찰하였다.

• Transactions on Electrical and Electronic Materials
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• 제6권5호
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• pp.225-228
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• 2005

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

• 접착 및 계면
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• 제11권3호
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• pp.120-125
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• 2010

UV-curable acrylic Pressure-sensitive adhesives (Acrylic PSAs) are used in many different parts in the world. A wafer manufacture process which is based on semiconductor industry is one thing. We have used acrylic PSAs whose thickness is different from $20{\mu}m$ to $30{\mu}m$ in wafer manufacture process so far. But as wafers become more thinner, acrylic PSAs are supposed to satisfy the requirements such as proper adhesion performance. The main purpose of this research is studying proper adhesion performance and UV-curing behavior of UV-curable acrylic PSAs with very thin thickness and then determining optimized conditions to raise the efficiency of thin wafer production. Acrylic PSAs contain 2-Ethylhexyl Acrylate (2-EHA), Acrylic Acid (AA) and Butyl Acrylate (BA). Ethyl acetate (EtAc) is used as solvent. The acrylic PSAs are obtained using solvent polymerization. Thickness of UV-curable acrylic PSAs is different from $10{\sim}30{\mu}m$. By peel strength and probe tack, adhesion performance and UV curing behavior of acrylic PSA are concerned.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.38-38
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• 2009

Wafer thickness of crystalline silicon is an important factor which decides a price of solar cell. PC1D was used to fix a condition that is required to get a high efficiency in a crystalline silicon solar cell using thin wafer($150{\mu}m$). In this simulation, base resistivity and emitter doping concentration were used as variables. As a result of the simulation, $V_{oc}$=0.6338(V), $I_{sc}$=5.565(A), $P_{max}$=2.674(W), FF=0.76 and efficiency 17.516(%) were obtained when emitter doping concentration is $5{\times}10^{20}cm^{-3}$, depth factor is 0.04 and sheet resistance is $79.76{\Omega}/square$.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 제35회 춘계학술대회
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• pp.310-316
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• 2002

In this study, the effects of oxide layer formed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with $1{\mu}m$ in coating thickness. AISI 52100 steel ball was used for the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction (XRD). Auger electron spectroscopy (AES), scanning electron microscopy (SEM) and sliding tests.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.11.1-11.1
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• 2011

We have developed a simple synthetic method for fabricating a wafer-scale colloidal crystal film of 2D crystals in a 1D stack based on a combination of two simple processes : the self-assembly of polystyrene (PS) nanospheres at the water-air interface and the layer-by-layer (LbL) scooping transfer technique. The main advantage of this approach is that it allows excellent control of the thickness (at a layer level) of the crystals and the formation of a vertical crack-free layer over a wafer-scale (4 inch). We investigate the optical and morphological properties of the PhC multilayers fabricated using various mono-sized colloidal crystals (250, 300, 350, 420, 580, 720, and 850 nm), and mixed binary colloidal crystals (300/350 and 250/350 nm).

• 전자공학회논문지A
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• 제31A권7호
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• pp.69-75
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• 1994

A very fine pattern formation process using double exposure is investigated, which can overcome the resolution limit of optical wafer stepper. The very fine pattern can be obtained by moving the edge profile of large pattern by means of moving the stepper stage. The simulation results show that the light transmittance decrease bellow 9%, and the contrast increase to 16.6% for the 0.3$\mu$m photoresist pattern exposeed by the double exposure using i-line wafer stepper. And the experimental results show that fine photoresist pattern as short as 0.2$\mu$m can be obtained without a loss of photoresist thickness. Also, it proves that the depth of focus for 0.3$\mu$m pattern is longer than $1.5\mu$m. And, the very fine negative photoresist pattern was formmed by using the double exposure technique and the image reversal process.

• 한국가시화정보학회지
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• 제14권2호
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• pp.25-30
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• 2016

The wafer temperature and its uniformity inside the LPCVD chamber were analyzed. The temperature uniformity at the end of the wafer load depends on the heat-insulating cap. The finite difference method was used to investigate the radiation and conduction heat transfer mechanisms, and the temperature field and heat diffusion in the LPCVD chamber was visualized. It was found that the temperature uniformity of the wafers could be controlled by the size and distance of the heat-insulating cap.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.383-385
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• 2013

반도체소자의 고속실현을 위해서 알루미늄배선에서 40% 가량 성능을 높이는 반면 제조비용은 30%까지 낮출 수 있는 구리를 선호하고 있으나, 식각이 잘 되지 않아 원하는 패턴으로 만들어 내기가 곤란한 공정기술의 어려움과 구리물질이 지닌 유독성문제를 가지고 있다. 기존의 식각기술로는 구리패턴을 얻을 수 없는 기술적 한계 때문에 화학.기계적 연마(CMP)를 이용한 평탄화와 연마를 통해서 구리배선을 얻는 다마스커스(Damascene)기술이 개발됐고 이를 이용한 구리배선기술이 현실적으로 가능하게 됐다. CMP를 이용한 평탄화 및 연마 공정에서 Wafer에 도포된 구리의 두께를 실시간으로 측정하여 정밀하게 제어할필요가 있는데, 본 논문에서는 와전류를 이용하여 옹고스트롬 단위의 두께를 실시간으로 측정하여 제어 하는 시스템구현에 대해 기술한다.

• E2M - 전기 전자와 첨단 소재
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• 제9권7호
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• pp.727-732
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• 1996

In the present paper, the Cu films 4.mu.m thick were deposited by RF magnetron sputtering method on Si wafer. The Cu films deposited at a condition of 100W, 10mtorr exhibited a low electrical resistivity of 2.3.mu..ohm..cm and densed microstructure, poor adhesion. The Cu films grown by 200W, 20mtorr showed a good adhesion property and higher electrical resistivity of 7.mu..ohm..cm because of porous columnar microstructure. Therefore, The Cu films were deposited by double layer deposition method using RF magnetron sputtering on Si wafer. The dependence of the electrical resistivity, adhesion, and reflectance in the CU films [C $U_{4-d}$(low resistivity) / C $U_{d}$(high adhesion) / Si-wafer] on the thickness of d has been investigated. The films formed with this deposition methods had the low electrical resistivity of about 2.6.mu..ohm..cm and high adhesion of about 700g/cm.m.m.