• 정보저장시스템학회논문집
• /
• 제1권2호
• /
• pp.175-181
• /
• 2005

SiOB is an essential part of slim optical pickup, where the silicon mirror, LD stand, silicon PD are integrated and LD is flip chip bonded. SiOB is fabricated with bulk micromachining. Especially the fabrication of silicon wafer with stepped concave areas has many extraordinary difficulties. As a matter of fact, experiences and knowledges are rare in the fabrication of the highly stepped silicon wafer. The difficulties occurring in the integration of PD and SiOB, and highly stepped patterning, and silicon mirror roughness and how-to-solve will be discussed.

• 전자공학회논문지
• /
• 제51권8호
• /
• pp.23-29
• /
• 2014

실리콘 태양전지 제조에 기판으로 사용되는 156 mm 실리콘 웨이퍼의 제작 공정에 있어서 제품 불량 및 성능 저하를 유발하는 웨이퍼 표면 오염원을 분석하였으며, 이를 제거하기 위한 오존수 세정에 대하여 실험하였다. 오염물질은 웨이퍼 절단 공정에서 사용되는 슬러리 및 세척액 속에 포함된 유기물과 소잉 와이어로부터 분리된 미세입자에 의해 형성되며, 오존수 세정공정을 통하여 제거할 수 있었다. 이 기술을 적용하면 태양전지용 웨이퍼를 저렴하고 효율적이며 친환경적으로 제조할 수 있다.

• 한국경영과학회지
• /
• 제18권1호
• /
• pp.119-126
• /
• 1993

We study a manufacturing process that is quite common in semiconductor wafer fabrication of semiconductor chip production. A machine is used to process a job consisting of J wafers. Each job requires a setup, and the i$_{th}$ setup for a job is sucessful with probability P$_{i}$. The setup is prone to failure, which results in the loss of expensive wafers. Therefore, a tiral run is first conducted on a small batch. If the set up is successful, the test is passed and the balance of the job can be processed. If the setup is unsuccessful, the exposed wafers are lost to scrap and the mask is realigned. The process then repeats on the balance of the job. We call this as send-ahead policy and consider general policies in which the number of wafers that are sent shead depend on the cost of the raw wafer, the sequence of success probabilities, and the balance of the job. We model this process and determine the expected number of good wafers per job,the expected time to process a job, and the long run average throughput. An algorithm to minimize the cost per good wafer subject to a demand constraint is provided.d.d.

• 조명전기설비학회논문지
• /
• 제22권6호
• /
• pp.148-155
• /
• 2008

본 논문에서는 웨이퍼 에지 노광장비에 핵심 부분인 웨이퍼의 편심오차의 측정알고리즘과 플랫/노치의 방향을 해석하는 알고리즘을 제안하였다. 또한 새로 제안된 알고리즘을 전산 시뮬레이션을 통해 그 유효성을 확인하였으며 제작된 웨이퍼 에지 노광기에 적용하여 실제 장비에 적용 가능함을 확인하였다. 제안된 알고리즘을 위해 필요한 웨이퍼 에지 위치 검출방식에 있어 과거의 접촉식 방법을 사용함으로서 발생하는 파티클의 오염을 제거하기 위해 선형 CCD 센서를 적용한 비접촉 방식의 데이터 측정법을 적용함으로서 파티클의 오염을 제어 할 수 있었다.

• 한국주조공학회지
• /
• 제33권4호
• /
• pp.157-161
• /
• 2013

A ribbon-type polycrystalline silicon wafer was directly fabricated from liquid silicon via a novel technique for both a fast growth rate and large grain size by exploiting gas pressure. Effects of processing parameters such as moving speed of a dummy bar and the length of the solidification zone on continuous casting of the silicon wafer were investigated. Silicon melt extruded from the growth region in the case of a solidification zone with a length of 1cm due to incomplete solidification. In case of a solidification zone wieh a length of 2 cm, on the other hand, continuous casting of the wafer was impossible due to the volume expansion of silicon derived from the liquid-solid transformation in solidification zone. Consequently, the optimal length of the solidification zone was 1.5 cm for maintaining the position of the solid-liquid interface in the solidification zone. The silicon wafer could be continuously casted when the moving speed of the dummy bar was 6 cm/min, but liquid silicon extruded from the growth region without solidification when the moving speed of the dummy bar was ${\geq}$ 9 cm/min. This was due to a shift of the position of the solid-liquid interface from the solidification zone to the moving area. The present study reports experimental findings on a new direct growth system for obtaining silicon wafers with both high quality and productivity, as a candidate for an alternate route for the fabrication of ribbon-type silicon wafers.

• 한국정밀공학회지
• /
• 제29권12호
• /
• pp.1285-1289
• /
• 2012

This study has been focused on application of ELID lapping process for mirror-surface machining of sapphire wafer. Sapphire wafer is a superior material with optic properties of high performance as light transmission, thermal conductivity, hardness and so on. High effective surface machining technology is necessary to use sapphire as various usages. The interval ELID lapping process has been set up for lapping of the sapphire material. According to the ELID lapping experimental results, it shows that 12.5 kg of load for lapping is most pertinent to ELID lapping. the surface of sapphire can be eliminated by metal bonded wheel with micron abrasives and the surface roughness of 60 nmRa can be gotten using grinding wheel of 2,000 mesh in 4.5 um, depth of cut. In this study, the chemical experiments after ELID grinding also has been conducted to check chemical reaction between workpiece and grinding wheel on ELID grinding process. It shows that the chemical reaction has not happened as the results of the chemical experiments.

• 센서학회지
• /
• 제1권2호
• /
• pp.131-145
• /
• 1992

본 논문은 SOI트랜스듀서 및 회로를 위해, Si 직접접합과 M-C국부연마법에 의한 박막SOI구조의 형성 공정을 기술한다. 또한, 이러한 박막SOI의 전기적 및 압저항효과 특성들을 SOI MOSFET와 cantilever빔으로 각각 조사했으며, bulk Si에 상당한다는 것이 확인되었다. 한편, SOI구조를 이용한 두 종류의 압력트랜스듀서를 제작 및 평가했다. SOI구조의 절연층을 압저항의 유전체분리층으로 이용한 압력트랜스듀서의 경우, $-20^{\circ}C$에서 $350^{\circ}C$의 온도범위에 있어서 감도 및 offset전압의 변화는 자각 -0.2% 및 +0.15%이하였다. 한편, 절연층을 etch-stop막으로 이용한 압력트랜스듀서에 있어서의 감도변화를 ${\pm}2.3%$의 표준편차 이내로 제어할 수 있다. 이러한 결과들로부터 개발된 SDB공정으로 제작된 SOI구조는 집적화마이크로트랜스듀서 및 회로개발에 많은 장점을 제공할 것이다.

• Journal of Mechanical Science and Technology
• /
• 제20권12호
• /
• pp.2025-2033
• /
• 2006

This paper presents, the design of a latch mechanism for wafer containers in a standard mechanical interface environment. For an integrated circuits fabrication factory, the standard mechanical interfaced wafer container is an effective tool to prevent wafers from particle contamination during wafer storage, transporting or transferring. The latch mechanism inside the container door is used to latch and further seal the wafer container for safety and air quality. Kinematic characteristics of the mechanism are established by analyzing the required functions of the mechanisms. Based on these characteristics, a methodology for enumerating feasible latch mechanisms is developed. New mechanisms with one degree-of-freedom and up to five links are generated. An optimum design is also identified with respect to the criteria pertinent to the application. The computer-aided simulation is also built to verify the design.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 1997년도 춘계학술대회 논문집
• /
• pp.921-926
• /
• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2000년도 춘계학술대회 논문집
• /
• pp.854-857
• /
• 2000

Chemical Mechanical Polishing(CMP) has been accepted as one of the essential processes for VLSI fabrication. However, as the polishing process continues, pad pores get to be glazed by polishing residues, which hinder the supply of new slurry. This defect makes removal rate decrease with a number of polished wafer and the desired within-chip planarity, within wafer and wafer-to-wafer nonuniformity are unable to be achieved. So, pad conditioning is essential to overcome this defect. The eletroplated diamond grit disk is used as the conventional conditioner, And alumina long fiber, the .jet power of high pressure deionized water and vacuum compression are under investigation. But, these methods have the defects like scratches on wafer surface by out of diamond grits, subsidences of pad pores by over-conditioning, and the limits of conditioning effect. To improve these conditioning methods. this paper presents the Characteristics of Ultrasonic conditioning aided by cavitation.