• Title/Summary/Keyword: Wafer fabrication

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A study on the real-time monitoring & control for wafer fabrication process (웨이퍼 가공공정 실시간 감시제어에 관한 연구)

  • 임성호;이근영;이범렬;한근희;최락만
    • 제어로봇시스템학회:학술대회논문집
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    • 1989.10a
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    • pp.421-426
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    • 1989
  • Many of semiconductor manufacturing companies persuit automation of wafer fabrication to improve the yields and quality of their products. Development of real-time control system for wafer fabrication and wafer/cassette automatic transfer-system is the most important part to achieve the purpose. In this paper, SECS protocol proposed by SEMI is briefly reviewed and an implementation method of real-time monitoring and control system is suggested as one of the possible ways for wafer fabrication automation. The system consists of process equipments supporting SECS.

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Performance Analysis of Scheduling Rules in Semiconductor Wafer Fabrication (반도체 웨이퍼 제조공정에서의 스케줄링 규칙들의 성능 분석)

  • 정봉주
    • Journal of the Korea Society for Simulation
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    • v.8 no.3
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    • pp.49-66
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    • 1999
  • Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

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Shift Scheduling in Semiconductor Wafer Fabrication (반도체 Wafer Fabrication 공정에서의 Shift 단위 생산 일정계획)

  • Yea, Seung-Hee;Kim, Soo-Young
    • IE interfaces
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    • v.10 no.1
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    • pp.1-13
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    • 1997
  • 반도체 Wafer Fabrication 공정은 무수한 공정과 복잡한 Lot의 흐름 등으로 다른 제조 형태에 비해 효율적인 관리가 대단히 어려운 부문이다. 본 연구는 반도체 Fab을 대상으로 주어진 생산 소요량과 목표 공기를 효율적으로 달성하기 위한 Shift 단위의 생산 일정계획을 대상으로 하였다. 특히, 전 공정 및 장비를 고려하기보다는 Bottleneck인 Photo 공정의 Stepper를 중심으로, 공정을 Layer단위로 묶어, 한 Shift에서 어떻게 Stepper를 할당하고 생산계획을 할 것인가를 결정하기 위한 2단계 방법론을 제시하고, Stepper 할당 및 계획에 필요한 3가지 알고리즘들을 제시하였다. 이 기법들을 소규모의 예제들에 대해 적용한 결과와 최적해와의 비교를 통하여 그 성능을 평가하였다.

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Critical review of retrospective exposure assessment methods used to associate the reproductive and cancer risks of wafer fabrication workers (반도체 웨이퍼 가공 근로자의 생식독성과 암 위험 역학연구에서 과거 노출평가 방법 고찰)

  • Park, Donguk;Lee, Kyungmoo
    • Journal of Korean Society of Occupational and Environmental Hygiene
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    • v.22 no.1
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    • pp.9-19
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    • 2012
  • Objectives: The aim of this study is to critically review the exposure surrogates and estimates used to associate health effects in wafer fabrication workers such as spontaneous abortion and cancer, as well as to identify the limitations of retrospective exposure assessment methods Methods: Epidemiologic and exposure-assessment studies of wafer fabrication operations in the semiconductor industry were collected. Retrospective exposure-assessment methods used in cancer risk and mortality and reproductive toxicity were reviewed. Results: Eight epidemiologic papers and two reports compared cancer risk among workers in wafer fabrication facilities in the semiconductor industry with the risk of the general population. Exposure surrogates used in those cancer studies were fabrication(vs. non-fabrication), employment duration, manufacturing eras, job title (operator vs. maintenance worker) and qualitative classifications of agents without assessing specific agent or job-specific exposure. In contrast, specific operation, job title and agents were used to classify the exposure of fabrication workers, contributing to finding a significant association with spontaneous abortion (SAB). Conclusion: Further epidemiologic studies of fabrication workers using more refined exposure assessment methods are warranted in order to examine the associations between fabrication work, environment, and specific agents with cancer risk or mortality as used in SAB epidemiologic studies.

Research on the WIP-based Dispatching Rules for Photolithography Area in Wafer Fabrication Industries

  • Lin, Yu-Hsin;Tsai, Chih-Hung;Lee, Ching-En;Chiu, Chung-Ching
    • International Journal of Quality Innovation
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    • v.8 no.2
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    • pp.132-146
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    • 2007
  • Constructing an effective production control policy is the most important issue in wafer fabrication factories. Most of researches focus on the input regulations of wafer fabrication. Although many of these policies have been proven to be effective for wafer fabrication manufacturing, in practical, there is a need to help operators decide which lots should be pulled in the right time and to develop a systematic way to alleviate the long queues at the bottleneck workstation. The purpose of this study is to construct a photolithography workstation dispatching rule (PADR). This dispatching rule considers several characteristics of wafer fabrication and influential factors. Then utilize the weights and threshold values to design a hierarchical priority rule. A simulation model is also constructed to demonstrate the effect of the PADR dispatching rule. The PADR performs better in throughput, yield rate, and mean cycle time than FIFO (First-In-First-Out) and SPT (Shortest Process Time).

Optimization for robot operations in cluster tools for concurrent manufacturing of multiple wafer types (복수 타입의 웨이퍼 혼류생산을 위한 클러스터 장비 로봇 운영 최적화)

  • Tae-Sun Yu;Jun-Ho Lee;Sung-Gil Ko
    • Journal of Industrial Technology
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    • v.43 no.1
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    • pp.49-55
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    • 2023
  • Cluster tools are extensively employed in various wafer fabrication processes within the semiconductor manufacturing industry, including photo lithography, etching, and chemical vapor deposition. Contemporary fabrication facilities encounter customer orders with technical specifications that are similar yet slightly varied. Consequently, modern fabrications concurrently manufacture two or three different wafer types using a cluster tool to maximize chamber utilization and streamline the flow of wafer lots between different process stages. In this review, we introduce two methods of concurrent processing of multiple wafer types: 1) concurrent processing of multiple wafer types with different job flows, 2) concurrent processing of multiple wafer types with identical job flows. We describe relevant research trends and achievements and discuss future research directions.

Statistical Design of Experiments and Analysis: Hierarchical Variance Components and Wafer-Level Uniformity on Gate Poly-Silicon Critical Dimension (통계적 실험계획 및 분석: Gate Poly-Silicon의 Critical Dimension에 대한 계층적 분산 구성요소 및 웨이퍼 수준 균일성)

  • Park, Sung-min;Kim, Byeong-yun;Lee, Jeong-in
    • Journal of Korean Institute of Industrial Engineers
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    • v.29 no.2
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    • pp.179-189
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    • 2003
  • Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

Direct Carrier System Based 300mm FAB Line Simulation (Direct 반송방식에 기반을 둔 300mm FAB Line 시뮬레이션)

  • Lee, Hong-Soon;Han, Young-Shin;Lee, Chil-Gee
    • Journal of the Korea Society for Simulation
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    • v.15 no.2
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    • pp.51-57
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    • 2006
  • Production environment of semiconductor industry is shifting from 200mm wafer process to 300mm wafer process. In the new era of semiconductor industry, FAB (fabrication) Line Automation is a key issue that semiconductor industry is facing in shifting from 200mm wafer fabrication to 300mm wafer fabrication. In addition, since the semiconductor manufacturing technologies are being widely spread and market competitions are being stiffened, cost-down techniques became basis of growth. Most companies are trying to reduce average cycle time to increase productivity and delivery time. In this paper, we simulated 300mm wafer fabrication semiconductor manufacturing process by laying great emphasis on reduce average cycle time.

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Scheduling Simulator for Semiconductor Fabrication Line (반도체 FAB의 스케줄링 시뮬레이터 개발)

  • Lee, Young-Hoon;Cho, Han-Min;Park, Jong-Kwan;Lee, Byung-Ki
    • IE interfaces
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    • v.12 no.3
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    • pp.437-447
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    • 1999
  • Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

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Retrospective Exposure Assessment of Wafer Fabrication Workers in the Semiconductor Industry (반도체 웨이퍼 가공 공정 역학 조사에서 과거 노출 평가 방법 고찰)

  • Park, Dong-Uk
    • Journal of Environmental Health Sciences
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    • v.37 no.1
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    • pp.12-21
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    • 2011
  • The objective of this study is to review retrospective exposure assessment methods used in wafer fabrication operations to determine whether adverse health effects including mortality or cancer incidence are related to employment in particular work activities and to recommend an appropriate approach for retrospective exposure assessment methods for epidemiological study. The goal of retrospective exposure assessment for such studies is to assign each study subject to a workgroup in such a way that differences in exposure within the workgroups are minimized, as well as to maximize the contrasts in exposure between workgroups. To reduce the misclassification of exposure and to determine if adverse health effects including mortality or cancer incidence are related to particular work activities of wafer fabrication workers, a minimum requirement of work history information on the wafer manufacturing eras, job and department at which they were exposed should be assessed. Retrospective assessment of the task that semiconductor workers performed should be conducted to determine not only the effect of a particular job on the development of adverse health effects including mortality or cancer incidence, but also to adjust for the healthy worker effect. In order to identify specific hazardous agents that may cause adverse health effects, past exposure to a specific agent or agent matrices should also be assessed.