• KIPS Transactions on Software and Data Engineering
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• v.12 no.3
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• pp.141-148
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• 2023

Accurate overlay metrology is essential to achieve high yields of semiconductor products. Overlay metrology performance is greatly affected by overlay target design and measurement method. Therefore, in order to improve the performance of the overlay target, measurement methods applicable to various targets are required. In this study, we propose a new algorithm that can measure image-based overlay. The proposed measurement algorithm can estimate the sub-pixel position by using a motion vector. The motion vector may estimate the position of the sub-pixel unit by applying a quadratic equation model through polynomial expansion using pixels in the selected region. The measurement method using the motion vector can calculate the stacking error in all directions at once, unlike the existing correlation coefficient-based measurement method that calculates the stacking error on the X-axis and the Y-axis, respectively. Therefore, more accurate overlay measurement is possible by reflecting the relationship between the X-axis and the Y-axis. However, since the amount of computation is increased compared to the existing correlation coefficient-based algorithm, more computation time may be required. The purpose of this study is not to present an algorithm improved over the existing method, but to suggest a direction for a new measurement method. Through the experimental results, it was confirmed that measurement results similar to those of the existing method could be obtained.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.6
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• pp.996-1002
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• 2013

This study addresses the development of a full duplex robotic system for transferring flat-panel display glass. We propose to accomplish this using a bidirectional linear transfer mechanism in place of the conventional rotary transfer mechanism. The developed full duplex robot comprises a driving part that carries the glass panel laterally, vertical part that can be moved up and down by means of a ball screw and linear motion guide arrangement, and hand part that slides by the cylinder of the driving part along the guide rail with a V-guide bearing attached to the bottom of the support. In addition, an alignment part prevents the hand part from derailing and holds the hand part while the driving part moves horizontally. The full duplex robot lifts and drives a glass panel directly while transferring it to the buffer and does not require rotational motion. Therefore, both transferring and stacking are realized with a single device. This device can be used in existing industrial facilities as an alternative to existing industrial robots in current as well as future process lines. The proposed full duplex robot is expected to save considerable amounts of time and space, and increase product throughput.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.5
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• pp.442-453
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• 2023

Tandem or multijunction solar cells (MJSCs) can convert sunlight into electricity with higher efficiency (η) than single junction solar cells (SJSCs) by dividing the solar irradiance over sub-cells having distinct bandgaps. The efficiencies of various common SJSC materials are close to the edge of their theoretical efficiency and hence there is a tremendous growing interest in utilizing the tandem/multijunction technique. Recently, III-V materials integration on a silicon substrate has been broadly investigated in the development of III-V on Si tandem solar cells. Numerous growth techniques such as heteroepitaxial growth, wafer bonding, and mechanical stacking are crucial for better understanding of high-quality III-V epitaxial layers on Si. As the choice of growth method and substrate selection can significantly impact the quality and performance of the resulting tandem cell and the terminal configuration exhibit a vital role in the overall proficiency. Parallel and Series-connected configurations have been studied, each with its advantage and disadvantages depending on the application and cell configuration. The optimization of both growth mechanisms and terminal configurations is necessary to further improve efficiency and lessen the cost of III-V on Si tandem solar cells. In this review article, we present an overview of the growth mechanisms and terminal configurations with the areas of research that are crucial for the commercialization of III-V on Si tandem solar cells.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.