• 한국생산제조학회지
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• 제22권2호
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• pp.310-317
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• 2013

In this paper, the contact pressure of the wafer and polishing pad for final polishing process for 300 mm-wafer were investigated through numerical analysis using FEM tool, ANSYS. The distribution of the contact pressure is one of main parameters which affects on the flatness and surface roughness of polished wafers. Two types of polishing head, a hard type head with ceramic disk and a soft type head with air bag were considered. The effects of the deformation and initial shape of table on the contact pressure were also examined. Both heads and tables were modeled as 3D finite element model from solid model, and the material properties of polishing pads and rubber plate for the air-bag head were obtained from tensile tests. The contact pressure deviation on wafer surface was smaller with air bag head than hard type head even when the table had form errors such as convex or concave. From this 3D analysis, it could be concluded that the air-bag head has better uniformity of the contact pressure on wafer. Also, the effects of inner diameter of air bag and radial clearance between wafer and retainer were investigated as view point of contact pressure concentration on the edge of wafer.

• 디지털콘텐츠학회 논문지
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• 제3권1호
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• pp.113-122
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• 2002

반도체와 관련한 실리콘웨이퍼의 평탄도는 양질의 웨이퍼를 보증하는 가장 중요한 요소이다. 따라서 평탄도(flatness)를 측정하고 제어하는 Polishing이라는 공정은 웨이퍼 생산의 여러 라인중 특별히 중요시 되는 과정이며 현재 이 공정에서는 담당 엔지니어가 웨이퍼의 모형을 모니터에서 육안으로 관찰하여 판단하고 평탄도를 높이기 위한 제어를 하고 있다. 그러나 사람에 의한 것이므로 많은 경험이 필요하고 일일이 체크해야하는 번거로움이 있다. 본 연구는 이러한 비효율적인 작업의 효율화를 위해 이루어 졌으며 Polishing 공정에 있어 평탄도를 사람이 아닌 시스템에 의해 자동으로 측정하여 제어하는 알고리즘을 제안한다. 여기서 제안한 시스템은 보간 다항식을 이용하여 웨이퍼 전역의 두께를 추정하고 Polishing공정에서 평탄도를 높이기 위해 제어 가능한 모형별로 분류할 수 있도록 하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.555-556
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• 2006

In recent years, the higher flatness level in wafer shape has been strictly demanded with a high integration of the semiconductor devices. It has become difficult for a conventional wafer preparing process to satisfy those demands. In order to meet those demands, surface grinding with in-feed grinder is adopted. In an in-feed grinding method, a chuck table fur fixing a semiconductor wafrr rotates on its rotation axis with a slight tilt angle to the rotation axis of a cup shaped grinding wheel and the grinding wheel in rotation moves down to grind the wafer. So, stability of the grinder structure is very important to aquire a wafer of good quality. This paper describes the features of the in-feed grinder and some FEM analysis results of the grinder structure.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1999년도 추계학술대회 논문집 - 한국공작기계학회
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• pp.525-529
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• 1999

A cone shape drum polisher was developed to make up for the demerits of conventional CMP apparatus. The developed equipment has several superiorities. First of all, it can achieve uniform velocity profile on all the contact line because of its shape and easy to control the amount of slurry at the position of use. The whole area of wafer surface is exposed to the visual area except the contact line between wafer and drum, hence we can detect polishing end point more easily than any other polishing equipments. Also it has additional merits such as small foot print and polishing load. Polishing characteristics were investigated by developed equipment.

• Tribology and Lubricants
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• 제32권4호
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• pp.119-124
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• 2016

In the sapphire wafering process, lapping is a crucial operation in order to reduce the damaged layer and achieve the target thickness. Many parameters, such as pressure, velocity, abrasive, slurry and plate, affect lapping characteristics. This paper presents an experimental investigation on the effect of the plate groove on the material removal rate and roughness of the wafer. We select the spiral pattern and rectangular type as the groove shapes. We vary the groove density by controlling the groove shape dimension, i.e., the groove width and pitch. As the groove density increases to 0.4, the material removal rate increases and gradually reaches a saturation point. When the groove density is low, the pressing load is mostly supported by the thick film, and only a small amount acts on the abrasives resulting to a low material removal rate. The roughness decreases on increasing the groove density up to 0.3 because thick film makes partial participations of large abrasives which make deep scratches. From these results, we could conclude that the groove affects the contact condition between the wafer and plate. At the same groove density, the pitch has more influence on reducing the film thickness than the groove width. By decreasing the groove density with a smaller pitch and larger groove width, we could achieve a high material removal rate and low roughness. These results would be helpful in understanding the groove effects and determining the appropriate groove design.

• 한국결정성장학회지
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• 제12권3호
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• pp.120-125
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• 2002

Si-wafers for solar cells were cast in a size of $50{\times}46{\times}0.5{\textrm}{mm}^3$ by vacuum casting method. The graphite mold coated by BN powder, which was to prevent the reaction of carbon with the molten silicon, was used. Without coating, the wetting and reaction of Si melt to graphite mold was very severe. In the case of BN coating, SiC was formed in the shape of tiny islands at the surface of Si wafer by the reaction between Si-melt and carbon of the graphite mold on the high temperature. The grain size was about 1 mm. The efficiency of Si solar cell was lower than that of Si solar cell fabricated on commercial single and poly crystalline Si wafer. The reason of low efficiency was discussed.

• 전자공학회논문지A
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• 제32A권3호
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• pp.134-142
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• 1995

We discovered that each distinct shape of the roof-shaped peaks of (111) facets, which are generated on (110) cross-section of the directly bonded (100) silicon wafer pairs after KOH etching, can be mapped to one of three conditions of the interfacial oxide existing at the bonding interface as follows. That is, thick solid line can be mapped to stabilization, thin solid line to disintegration, and thin broken line to spheroidization. also we confirmed that most of the interfacial oxides of a well-aligned wafer pairs were disintegrated and spheroidized through high-temperature annealing process above 900$^{\circ}$C while the oxide was stabilized persistently when two wafers are bonded rotationally around their common axis perpendicular to the wafer planes.

• 마이크로전자및패키징학회지
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• 제7권2호
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• pp.55-62
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• 2000

Si-wafer에 단면 코팅된 UBM(Under Bump Metallurgy)의 젖음성을 Sn-Pb 솔더에서 평가하기 위하여 wetting balance 법을 사용하였다. 단면 코팅된 UBM의 젖음곡선은 양면 코팅된 시편의 젖음 곡선과 비교할 때, 젖음곡선의 모양이 비슷하고 젖음곡선을 특징짓는 변수들의 온도에 대한 변화경향이 일치하였다. 단면 코팅된 금속층의 젖음성을 젖음곡선으로부터 정의한 새로운 젖음 지수 $F_{min}$, $F_{s}t_{s}$로 평가할 수 있었다. Au/Cu/Cr UBM은 젖음시간의 측면에서 Au/Ni/Ti UBM보다 젖음성이 우수하였다 Si-wafer에 단면 코팅된 UBM과 Sn-Pb 솔더의 접촉각을 $F_{s}$와 기울어짐각을 측정하고 메니스커스의 정적상태에서 힘의 평형으로부터 유도된 식을 이용하여 계산할 수 있었다.

• 한국주조공학회지
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• 제33권2호
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• pp.69-74
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• 2013

Silicon (Si) wafer was grown by using direct growth from Si melt and contaminations of wafer during the process were investigated. In our process, BN was coated inside of all graphite parts including crucible in system to prevent carbon contamination. In addition, coated BN layer enhance the wettability, which ensures the favorable shape of grown wafer by proper flow of Si melt in casting mold. As a result, polycrystalline silicon wafer with dimension of $156{\times}156$ mm and thickness of $300{\pm}20$ um was successively obtained. There were, however, severe contaminations such as BN and SiC on surface of the as-grown wafer. While BN powders were easily removed by brushing surface, SiC could not be eliminated. As a result of BN analysis, C source for SiC was from binder contained in BN slurry. Therefore, to eliminate those C sources, additional flushing process was carried out before Si was melted. By adding 3-times flushing processes, SiC was not detected on the surface of as-grown Si wafer. Polycrystalline Si wafer directly grown from Si melt in this study can be applied for the cost-effective Si solar cells.

• 한국진공학회지
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• 제5권2호
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• pp.113-118
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• 1996

Aligning a cathode tip at the center of a gate hole is important in gated filed emission devices. We have fabricated a silicon field emitter using a following process so that a cathode and a gate hole are automatically aligned . After forming silicon tips on a silicon wafer, the wafer was covered with the $SiO_2$, gate metal, and photoresistive(PR) films. Because of the viscosity of the PR films, a spot where cathode tips were located protruded above the surface. By ashing the surface of the PR film, the gate metal above the tip apex was exposed when other area was still covered with the PR film. The exposed gate metal and subsequenlty the $SiO_2$ layer were selectively etched. The result produced a field emitter in which the gate film was in volcano shape and the cathode tip was located at the center of the gate hole. Computer simulation showed that the volcano shape and the cathode tip was located at the center of the gat hole. Computer simulation showed that the volcano shape emitter higher current and the electron beam which was focused better than the emitter for which the gate film was flat.