• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.5-6
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• 2009

In this paper, plasma ion implant is performed with $PH_3$ gas diluted by helium gas on P-type Si wafer (100). Spike Rapid Thermal Processing(RTP) annealing performed for 30~60 sec from $800\;^{\circ}C$ to $1000\;^{\circ}C$ in $N_2+O_2$ ambient. Crystalline defect is analyzed by Transmission Electron Microscope(TEM) and Double crystal X-ray Diffraction(DXRD). Contact resistivity($\rho c$), contact resistance(Rc) and sheet resistance(Rs) are analyzed by measuring Transfer Length Method(TLM) using 4155C analysis. As annealing temperature increase, Rs decrease and ${\rho}c$ and Rc increase at temperature higher than $850\;^{\circ}C$. We achieve low Rs, ${\rho}c$ and Rc with Plasma ion implant and spike RTP.

• 한국정밀공학회지
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• 제9권2호
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• pp.22-28
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• 1992

This paper is studied about the method to measure the fine scratches on the mirror surfaces, such as the silicon wafer and magnetic memory disk by the optical measuring method. The theoretical background of this analysis is based upon the light scattering theory developed by Beckmann. In this analysis, the roughness in fine scratches is not considered because the aberage roughness is very small compared with the size of fine scratches. Empasis is on quantilaive method of fine scratches by non-contact method. Experiments are followed by the image processing system attached to the CCD Camera. As a results, I propose the new method to measure the size of the fine scratches from the parameters obtained by the computer simulation and experiments.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.409-412
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• 1998

In this paper, we present an $H^2$ controller design of RTP(rapid thermal processing) systems satisfying robust stability and performance using weighted mixed sensitivity minimization. In industrial fields, RTP system is widely used for improving the oxidation and the annealing in semiconductor manufacturing process. The main control factors are temperature control of wafer and uniformity has been solved by PID control method. Because the reference inputs of RTP are ramp, we improve performance of RTP system by the design of $H^2controller$ using the weighted mixed sensitivity function. Also we compare $H^2controller$ with PID controller in terms of performance. An example is proposed to show the validity of proposed method.

• 동력기계공학회지
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• 제3권4호
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• pp.57-62
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• 1999

The microaccelerometer using a tunnelling current effect concept has the potential of high performance, although it requires slightly complex signal-processing circuit for servo-system. The paddle of micro accelerometer is pulled to have the gap width of about 2nm which almost allows the flow tunnelling current. This paper demonstrates at capacitor of microaccelerometer the use of the coupled thermo-electric analysis for voltage, current, heat flux and Joule heating then tunnelling current flows. Two electrodes are applied to the microaccelerometer producing a unform difference of temperature gradient and electric potential between the paddle and the substrate.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 추계학술대회 논문집
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• pp.1376-1379
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• 2004

This study is designed integration and control system of GaAs bonding system consisted of multi-processing using DeviceNet and GEM-Protocol. Developing bonding system is composed of resin coating, pre-baking pre-aligner, bonding, material handler(flip robot), and wafer cassette, etc. This system has process-fluent of each a process and share information using GEM-protocol. This study devised virtual bonding simulator to control and to monitor bonding system efficiently. Also we can verify optimizing of system previously through a virtual bonding simulator.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.65-65
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• 2003

Chemical mechanical polishing (CMP) is one of the most important processes in recent ULSI (Ultra Large Scale Integrated Circuit) manufacturing technology. Recently, ceria slurries with surfactant have recently been used in STI-CMP,[1] became they have high oxide-to-nitride removal selectivity and widen the processing margin The role of the abrasives, however, on the effect of planarization on STI-CMP is not yet clear. In this study, we investigated how the crystal characteristic affects the planarization efficiency of wafer surface with controlling crystallite size and poly crystalline abrasive size independently.

• Transactions on Electrical and Electronic Materials
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• 제15권6호
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• pp.344-347
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• 2014

This study was carried out on DLC thin film deposition technology used in infrared optical system production as a method of reducing the shape changes of the molding core and the consequent loss of life. Experiments on the deposition on silicon wafer and tungsten carbide used as a substrate for molding core were conducted at each processing condition using a filtered arc system, and it was found that the surface and mechanical properties were of the greatest quality when the substrate bias voltage of -150 V was used. In addition, it was confirmed that the PV and Ra characteristics were improved by the deposition of the DLC thin film.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.1054-1056
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• 2002

High temperature Kermal diffusion from $POCl_3$ source usually used for conventional process through put of a cell manufacturing line and potentially reduce cell efficiency through bulk like time degradation. To fabricate high efficiency solar cells with minimal thermal processing, spin-on-doping(SOD) technique can be employed to emitter diffusion of a silicon solar cell. A technique is presented to emitter doping of a mono-crystalline solar cell using spin-on doping (SOD). Moreover it is shown that the sheet resistance variation with RTA temperature and time fer mono-crystalline and multi-crystalline silicon samples. This novel SOD technique was successfully used to produces 11.3% efficiency l04mm by 104mm size mono-crystalline silicon solar cells.

• Journal of Korean Vacuum Science & Technology
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• 제6권3호
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• pp.120-125
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• 2002

The aim of the present work is to optimized the annealing parameter in both front and back screen printed contacts realization on p-type multicrystalline silicon and with phosphorus diffused. The RTA treatments were carried out at various temperatures from 600 to 850$\^{C}$ and annealing time ranging from 3 min to 5 min in air, O$_2$and N$_2$ ambiance. The contacts parameters are obtained according to Transmission Line Model measurements. A good RTA cycle is obtained with a temperature plateau of 700$\^{C}$-750$\^{C}$ and annealing ambiance of air. Several processing parameters required for good cell efficiency are discussed with an emphasis placed on the critical role of the glass frit in the aluminum paste. A anamolus behaviour of Aluminum n-doping on p-type Si wafer, contact at high temperature have also been studied.

• 대한전자공학회논문지SD
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• 제46권10호
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• pp.25-30
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• 2009

오존을 이용하여 PR 박리에 사용된 에틸렌 카보네이트계 박리 세정제를 재이용할 수 있는 기술에 대하여 연구함으로써 향후 고성능-저가격의 반도체, LCD 제조에서의 PR 박리 및 세정 공정에 적용할 수 있는 핵심 공정기술을 확보하였다. 이 기술을 적용하면 반도체 웨이퍼 및 LCD 평판의 PR 박리 세정을 보다 빠르고 저렴한 비용으로 수행할 수 있으므로 반도체 및 LCD 제작공정의 생산성을 향상시킬 수 있다.