• Journal of the Korean Society for Precision Engineering
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• v.14 no.9
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• pp.68-79
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• 1997

A six DOF fine manipulator based on magnetic levitation is developed. Since most of magnetic levitation system are inherently unstable, a proposed magnetically levitated fine manipulator is implemented by use of an antagonistic structure to increase stability. From mathematical modeling and experiment, the equations of motion are derived. In addition, a six DOF sensing system is implemented by use of three 2-axis PSD sensors. A model reference-$H_{\infty}$ controller is applied to the system for the position control, In application of the fine manipulator, a wafer probing system is proposed to identify nonfunctional circuts. The probing system requires compliance to avoid destruction of DUT(device under test). A feedfor- ward-PD controllers are presented by the terms of the position accuracy, the settling time and the force accuracy.y.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.38 no.4
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• pp.159-167
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• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1023-1028
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• 2012

A MMIC (Monolithic Microwave Integrated Circuit) mixer chip using the Schottky diode of an GaAs p-HEMT process has been developed for the I/Q demodulator of non-contact near field microwave probing system. A single balanced mixer type is adopted to achieve simple structure of the I/Q demodulator. A quadrature hybrid coupler and a quarter wavelength transmission line for 180 degree hybrid are realized with lumped elements of MIM capacitor and spiral inductor to reduce the mixer chip size. According to the on-wafer measurement, this MMIC mixer covers RF and LO frequencies of 1650MHz to 2050MHz with flat conversion loss. The MMIC mixer with miniature size of $2.5mm{\times}1.7mm$ demonstrates conversion loss below 12dB for both variations of RF and LO frequencies, LO-to-IF isolation above 43dB and RF-to-IF isolation above 23dB, respectively.

• Journal of the Korean Society for Nondestructive Testing
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• v.14 no.4
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• pp.237-243
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• 1995

We have studied methods of detecting attenuation of solid materials such as silicon wafer and piezoelectric $LiTaO_3$ by means of optical probing techniques. We have performed measurements of surface acoustic waves(SAW) generated from 90 degree wedge type transducer and also from inter-digital transducers(IDT). SAW of 20.0 MHz was generated on a silicon wafer from the 90 degree wedge type transducer and those of 20.8 and 14.5 MHz are generated on a $LiTaO_3$ from the IDT. Then any surface-corrugation resulted from the above SAW was investigated by He-Ne laser beams. We projected laser beams, which were modulated by an optical chopper, on the SAW of the same frequency and then measured the scattered beam by the lock-in amplifier. We modulated and synchronized both SAW and the incident laser beam as well as the phase sensitive detector(PSD) to the same frequency in order to simplify our measurement system. We obtained the attenuation coefficients of SAW to be $0.62{\sim}0.75dB/mm$(from IDT1, 20.8 MHz), and $0.60{\sim}0.72dB/mm$(from IDT2, 14.5 MHz), $0.83{\sim}1.28dB/mm$(from the wedge type), respectively.

• Korean Journal of Materials Research
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• v.11 no.7
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• pp.556-561
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• 2001

We prepared a new a SOS(silicon-on-silicide) wafer pair which is consisted of Si(100)/1000$\AA$-NiSi Si (100) layers. SOS can be employed in MEMS(micro- electronic-mechanical system) application due to low resistance of the NiSi layer. A thermally evaporated $1000\AA$-thick Ni/Si wafer and a clean Si wafer were pre-mated in the class 100 clean room, then annealed at $300~900^{\circ}C$ for 15hrs to induce silicidation reaction. SOS wafer pairs were investigated by a IR camera to measure bonded area and probed by a SEM(scanning electron microscope) and TEM(transmission electron microscope) to observe cross-sectional view of Si/NiSi. IR camera observation showed that the annealed SOS wafer pairs have over 52% bonded area in all temperature region except silicidation phase transition temperature. By probing cross-sectional view with SEM of magnification of 30,000, we found that $1000\AA$-thick uniform NiSi layer was formed at the center area of bonded wafers without void defects. However we observed debonded area at the edge area of wafers. Through TEM observation, we found that $10-20\AA$ thick amourphous layer formed between Si surface and NiSix near the counter part of SOS. This layer may be an oxide layer and lead to degradation of bonding. At the edge area of wafers, that amorphous layer was formed even to thickness of $1500\AA$ during annealing. Therefore, to increase bonding area of Si NiSi ∥ Si wafer pairs, we may lessen the amorphous layers.