• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.175-181
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• 2005

SiOB is an essential part of slim optical pickup, where the silicon mirror, LD stand, silicon PD are integrated and LD is flip chip bonded. SiOB is fabricated with bulk micromachining. Especially the fabrication of silicon wafer with stepped concave areas has many extraordinary difficulties. As a matter of fact, experiences and knowledges are rare in the fabrication of the highly stepped silicon wafer. The difficulties occurring in the integration of PD and SiOB, and highly stepped patterning, and silicon mirror roughness and how-to-solve will be discussed.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.23-29
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• 2014

We have studied on ozonate water cleaning mechanisms to apply in manufacturing process of 156 mm silicon wafer which is used in the solar cell fabrication. We have analyzed contamination sources on wafer surface which causes poor quality and performance of products in fabrication process, and examined cleaning process using ozonate water to eliminate it. Contamination sources consist of remaining material like organic matter in slurry and detergent and particles in sawing wire. Using this novel technology it is possible for the solar cell wafer to clean with low cost, high performance, and eco-friendly.

• Journal of the Korean Operations Research and Management Science Society
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• v.18 no.1
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• pp.119-126
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• 1993

We study a manufacturing process that is quite common in semiconductor wafer fabrication of semiconductor chip production. A machine is used to process a job consisting of J wafers. Each job requires a setup, and the i$_{th}$ setup for a job is sucessful with probability P$_{i}$. The setup is prone to failure, which results in the loss of expensive wafers. Therefore, a tiral run is first conducted on a small batch. If the set up is successful, the test is passed and the balance of the job can be processed. If the setup is unsuccessful, the exposed wafers are lost to scrap and the mask is realigned. The process then repeats on the balance of the job. We call this as send-ahead policy and consider general policies in which the number of wafers that are sent shead depend on the cost of the raw wafer, the sequence of success probabilities, and the balance of the job. We model this process and determine the expected number of good wafers per job,the expected time to process a job, and the long run average throughput. An algorithm to minimize the cost per good wafer subject to a demand constraint is provided.d.d.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.148-155
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• 2008

This study presents a process control of the wafer edge exposure (WEE) used in 300[mm] wafer environment. WEE, as a key module of the overall track system (coater and developer) for making patterns on wafer, is a system to expose the UV-ray on the wafer to remove a photo resist around edge of the wafer. It can measure, memorize and control the distance and angles from wafer center to edge. Recently in the 300[mm] semiconductor fabrication, the track system strongly requires that WEE station has a controller with high throughput and accuracy to increase process efficiency. We have designed and developed the controller, and present here a WEE control algorithm and experimental results.

• Journal of Korea Foundry Society
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• v.33 no.4
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• pp.157-161
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• 2013

A ribbon-type polycrystalline silicon wafer was directly fabricated from liquid silicon via a novel technique for both a fast growth rate and large grain size by exploiting gas pressure. Effects of processing parameters such as moving speed of a dummy bar and the length of the solidification zone on continuous casting of the silicon wafer were investigated. Silicon melt extruded from the growth region in the case of a solidification zone with a length of 1cm due to incomplete solidification. In case of a solidification zone wieh a length of 2 cm, on the other hand, continuous casting of the wafer was impossible due to the volume expansion of silicon derived from the liquid-solid transformation in solidification zone. Consequently, the optimal length of the solidification zone was 1.5 cm for maintaining the position of the solid-liquid interface in the solidification zone. The silicon wafer could be continuously casted when the moving speed of the dummy bar was 6 cm/min, but liquid silicon extruded from the growth region without solidification when the moving speed of the dummy bar was ${\geq}$ 9 cm/min. This was due to a shift of the position of the solid-liquid interface from the solidification zone to the moving area. The present study reports experimental findings on a new direct growth system for obtaining silicon wafers with both high quality and productivity, as a candidate for an alternate route for the fabrication of ribbon-type silicon wafers.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.12
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• pp.1285-1289
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• 2012

This study has been focused on application of ELID lapping process for mirror-surface machining of sapphire wafer. Sapphire wafer is a superior material with optic properties of high performance as light transmission, thermal conductivity, hardness and so on. High effective surface machining technology is necessary to use sapphire as various usages. The interval ELID lapping process has been set up for lapping of the sapphire material. According to the ELID lapping experimental results, it shows that 12.5 kg of load for lapping is most pertinent to ELID lapping. the surface of sapphire can be eliminated by metal bonded wheel with micron abrasives and the surface roughness of 60 nmRa can be gotten using grinding wheel of 2,000 mesh in 4.5 um, depth of cut. In this study, the chemical experiments after ELID grinding also has been conducted to check chemical reaction between workpiece and grinding wheel on ELID grinding process. It shows that the chemical reaction has not happened as the results of the chemical experiments.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• Journal of Mechanical Science and Technology
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• v.20 no.12
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• pp.2025-2033
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• 2006

This paper presents, the design of a latch mechanism for wafer containers in a standard mechanical interface environment. For an integrated circuits fabrication factory, the standard mechanical interfaced wafer container is an effective tool to prevent wafers from particle contamination during wafer storage, transporting or transferring. The latch mechanism inside the container door is used to latch and further seal the wafer container for safety and air quality. Kinematic characteristics of the mechanism are established by analyzing the required functions of the mechanisms. Based on these characteristics, a methodology for enumerating feasible latch mechanisms is developed. New mechanisms with one degree-of-freedom and up to five links are generated. An optimum design is also identified with respect to the criteria pertinent to the application. The computer-aided simulation is also built to verify the design.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.05a
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• pp.854-857
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• 2000

Chemical Mechanical Polishing(CMP) has been accepted as one of the essential processes for VLSI fabrication. However, as the polishing process continues, pad pores get to be glazed by polishing residues, which hinder the supply of new slurry. This defect makes removal rate decrease with a number of polished wafer and the desired within-chip planarity, within wafer and wafer-to-wafer nonuniformity are unable to be achieved. So, pad conditioning is essential to overcome this defect. The eletroplated diamond grit disk is used as the conventional conditioner, And alumina long fiber, the .jet power of high pressure deionized water and vacuum compression are under investigation. But, these methods have the defects like scratches on wafer surface by out of diamond grits, subsidences of pad pores by over-conditioning, and the limits of conditioning effect. To improve these conditioning methods. this paper presents the Characteristics of Ultrasonic conditioning aided by cavitation.