• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1121-1124
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• 2001

In this study, we verify th effects of pattern density on interlayer dielectric chemical mechanical polishing process based on the analysis of Preston's equation and confirm this analysis by several experiments. Appropriate modeling equation, transformed form Preston's equations used in glass polishing, will be suggested and described the effects of this modeling during pattern wafer ILD CMP. Results indicate that the modeling is well agreed to middle density structure of the die in pattern wafer, but has some error in low and high density structure of the die. Actually, the die used in Fab, was designed to have a appropriate density, therefore this modeling will be suitable for estimating the results of ILD CMP.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.566-569
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• 2001

Hot Plate is the major unit that it used to remove damp of wafer surface, to strength adhesion of photoresist(PR) and to bake coated PR in FAB process of semiconductor. It is necessary to guarantee the performance of Hot Plate(HP). Therefore, in this study designed and developed the reliability system of HP to measure and estimated thermal uniformity and flatness in temperature setting amplitude $0~250^{\circ}C$. We developed the techniques that measures and analyzes thermal uniformity using infrared thermal vision, and compensates measuring error of flatness using laser displacement sensor. For measuring flatness, we specially makes the measurement stage of 3 axes which adopts the precision encoder. The allowable error of measuring technique is less than thermal uniformity, $\pm 0.1^{\circ}C$ and flatness, $\pm 1mm$. It is expected that the developed system can measure from $\Phi$210(wafer 8") to $\Phi$356(wafer 12") and also can be used in performance test of the Cool Plate and industrial heater, etc.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.1
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• pp.196-203
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• 2002

Generally, non-uniformity and removal rate are important factors on measurements of both wafer and die scale. In this study, we verify the effects of the pressure and relative velocity on the results of the chemical mechanical polishing and the effect of pattern density on inter layer dielectric chemical mechanical polishing of patterned wafer. We suggest an appropriate modeling equation, transformed from Preston\`s equations which was used in glass polishing, and simulate the removal rate of patterned wafer in chemical mechanical polishing. Results indicate that the pressure and relative velocity are dominant factors for the chemical mechanical polishing and pattern density effects on removal rate of pattern wafers in die scale. The modeling is well agreed to middle and low density structures of the die. Actually, the die used in Fab. was designed to have an appropriate density, therefore the modeling will be suitable for estimating the results of ILD CMP.

• International Journal of Quality Innovation
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• v.9 no.3
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• pp.71-91
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• 2008

The definition of cycle time is the time from the wafer start to the wafer output. It usually takes one or two months to get the product since customer decides to produce it. The cycle time is a critical factor for customer satisfaction because it represents the response time to the market. Long cycle time reflects the ineffective investment for the capital. The cycle time is very important for foundry because long cycle time will cause customer unsatisfied and the order loss. Consequently, all of the foundries put lots of human source in the cycle time improvement. Usually, we make decisions based on the experience in the cycle time management. We have no mechanism or theory for cycle time management. We do work-in-process (WIP) management based on turn rate and standard WIP (STD WIP) set by experiences. But the experience didn't mean the optimal solution, when the situation changed, the cycle time or the standard WIP will also be changed. The experience will not always be applicable. If we only have the experience and no mechanism, management will not be work out. After interview several foundry fab managers, all of the fab can't reflect the situation. That is, all of them will have an impact period after product mix or utilization varied. In this study, we want to develop a formula for standard WIP and use statistical process control (SPC) concept to set WIP upper/lower limit level. When WIP exceed the limit level, it will trigger action plans to compensate WIP Profile. If WIP Profile balances, we don't need too much WIP. So WIP level could be reduced and cycle time also could be reduced.

• Journal of Intelligence and Information Systems
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• v.15 no.4
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• pp.213-224
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• 2009

This paper describes a real-time scheduling system re-construction project for automated manufacturing at a 300mm wafer fab of Korean semiconductor manufacturing company. During executing this project, for each main operation such as clean, diffusion, deposition, photolithography, and metallization, each adopted scheduling algorithm was developed, and then those were implemented in a real-time scheduling system. In this paper, we focus on the scheduling algorithms and real-time scheduling system for clean and diffusion operations, that is, a serial-process block with the constraint of limited queue time and batch processors. After this project was completed, the automated manufacturing utilizations of clean and diffusion operations became around 91% and 83% respectively, which were about 50% and 10% at the beginning of this project. The automated manufacturing system reduces direct operating costs, increased throughput on the equipments, and suggests continuous and uninterrupted processings.

• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.219-225
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• 2009

The primary purpose of this study is to build computer models referring overall flow of complex and various semiconductor wafer manufacturing process and to implement a educational model which operates with a presentation tool showing device design. It is important that Korean semiconductor industries secure high competitive power on efficient manufacturing management and to develop technology continuously. Models representing the FAB processes and the functions of each process are developed for Seoul National University Semiconductor Research Center. However, it is expected that the models are effective as visually educational tools in Korean semiconductor industries. In addition, it is anticipated that these models are useful for semiconductor process courses in academia. Scalability and flexibility allow semiconductor manufacturers to customize the models and perform simulation education. Subsequently, manufacturers save budget.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.8
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• pp.180-186
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• 2002

Hot Plate is the major unit that it used to remove damp of wafer surface, to strength adhesion of photoresist (PR) and to bake coated PR in FAB process of semiconductor. The badness of Hot Plate (HP) has directly influence upon the performance of wafer, it is necessary to guarantee the performance of HP. In this study, a reliability evaluation system has been designed and developed, which is to measure and to estimate thermal uniformity and flatness of HP in range of temperature 0~$250^\circC$. This system has included the techniques which measures and analyzes thermal uniformity using infrared thermal vision, and which compensates measuring error of flatness using laser displacement sensor For measuring flatness, a measurement stage of 3 axes are developed which adapts the precision encoder. The allowable error of this system in respect of thermal uniformity is less $than\pm0.1^\circC$ and in respect of flatness is less $than\pm$1mm . It is expected that the developed system can measure from $\Phi200mm\;(wafer 8＂)\;to\;\Phi300mm$ (wafer 12＂) and also can be used in performance test of the Cool Plate and industrial heater, etc.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1965-1967
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• 1999

We have investigated the electrical characteristics of the poly-Si TFT's with the novel gate insulator structure. The gate insulator makes the offset region to reduce leakage current, and the electrical characteristics are obtained by employing Virtual Wafer Fab. simulator. As increases the gate insulator thickness above the offset region of this structure from $0{\AA}$ to $2000{\AA}$, the OFF state current at $V_G$=10V decrease by two orders in magnitude while ON state current doesn't decrease significantly. ON/OFF current ratios for conventional device and the proposed device with $2000{\AA}$ gate insulator thickness are $1.68{\times}10^5$ and $1.07{\times}10^7$, respectively.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.269-273
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• 2001

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. In this paper, we propose Stand Alone layout and In-Line layout are analyzed and compared while varying number of device variable changes. The comparison is performed through simulation using ProSys; a window 98 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, In-Line layout is more efficient in terms of production quantity. However, as the number of device variable change is more than 14 titles, Stand Alone layout prevails over In-Line layout.

• Safety and Health at Work
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• v.2 no.3
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• pp.210-217
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• 2011

Objectives: The purpose of this study was to measure the concentration of volatile organic compound (VOC)s originated from the chemicals used and/or derived from the original parental chemicals in the photolithography processes of semiconductor manufacturing factories. Methods: A total of four photolithography processes in 4 Fabs at three different semiconductor manufacturing factories in Korea were selected for this study. This study investigated the types of chemicals used and generated during the photolithography process of each Fab, and the concentration levels of VOCs for each Fab. Results: A variety of organic compounds such as ketone, alcohol, and acetate compounds as well as aromatic compounds were used as solvents and developing agents in the processes. Also, the generation of by-products, such as toluene and phenol, was identified through a thermal decomposition experiment performed on a photoresist. The VOC concentration levels in the processes were lower than 5% of the threshold limit value (TLV)s. However, the air contaminated with chemical substances generated during the processes was re-circulated through the ventilation system, thereby affecting the airborne VOC concentrations in the photolithography processes. Conclusion: Tens of organic compounds were being used in the photolithography processes, though the types of chemical used varied with the factory. Also, by-products, such as aromatic compounds, could be generated during photoresist patterning by exposure to light. Although the airborne VOC concentrations resulting from the processes were lower than 5% of the TLVs, employees still could be exposed directly or indirectly to various types of VOCs.