Browse > Article

The Study of the Cycle Time Improvement by Work-In-Process Statistical Process Control Method for IC Foundry Manufacturing  

Lin, Yu-Cheng (Department of Industrial Engineering and Management National Chiao-Tung University)
Tsai, Chih-Hung (Department of Industrial Engineering and Management Ta-Hwa Institute of Technology)
Li, Rong-Kwei (Department of Industrial Engineering and Management National Chiao-Tung University)
Chen, Ching-Piao (Department of Industrial Engineering and Management Ta-Hwa Institute of Technology)
Chen, Hsien-Ching (Center for General Education, Chung-Hua University)
Publication Information
International Journal of Quality Innovation / v.9, no.3, 2008 , pp. 71-91 More about this Journal
Abstract
The definition of cycle time is the time from the wafer start to the wafer output. It usually takes one or two months to get the product since customer decides to produce it. The cycle time is a critical factor for customer satisfaction because it represents the response time to the market. Long cycle time reflects the ineffective investment for the capital. The cycle time is very important for foundry because long cycle time will cause customer unsatisfied and the order loss. Consequently, all of the foundries put lots of human source in the cycle time improvement. Usually, we make decisions based on the experience in the cycle time management. We have no mechanism or theory for cycle time management. We do work-in-process (WIP) management based on turn rate and standard WIP (STD WIP) set by experiences. But the experience didn't mean the optimal solution, when the situation changed, the cycle time or the standard WIP will also be changed. The experience will not always be applicable. If we only have the experience and no mechanism, management will not be work out. After interview several foundry fab managers, all of the fab can't reflect the situation. That is, all of them will have an impact period after product mix or utilization varied. In this study, we want to develop a formula for standard WIP and use statistical process control (SPC) concept to set WIP upper/lower limit level. When WIP exceed the limit level, it will trigger action plans to compensate WIP Profile. If WIP Profile balances, we don't need too much WIP. So WIP level could be reduced and cycle time also could be reduced.
Keywords
Foundry; Manufacturing Cycle Time; Delivery; Dispatch; Work-in-Process Management;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Chen, S. H.(2006), "fluidics of IC manufacturing maintaining work-in-process spread around workstation uniformly," master's thesis, Tung-Hai University, Taiwan
2 Goldratt, Eliyahu M.(2006), "The Strategy and Tactic trees-Consumer Goods-Viable Vision implementations," TOC Insights 2006
3 Levitt, M. E. and J. A. Abraham(1990), "Just-In-Time Methods for Semiconductor Manufacturing," IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 3-9
4 Lou, S. and P. W. Kager(1989), "A Robust Production Control Policy for VLSI Wafer Fabrication," IEEE Transactions on Semiconductor Manufacturing, Vol. 2, No. 4, pp. 159-164   DOI   ScienceOn
5 Miller, D. J.(1990), "Simulation of a semiconductor manufacturing line," Communication of The ACM, Vol. 33, No. 10, pp. 99-109   DOI
6 Wu, H. H. and Li, R. K.(2003), "Drum-Buffer-Rope Scheduling and management technology," Chuan-Hua Technology Books, Taiwan
7 Malmstrom, C.(1997), "Though Love: Real-time Planning and Scheduling at Philips Semiconductor," Manufacturing System, pp. 76-78
8 Hsu, F. N.(2007), "Flow control design of IC manufacturing accelerating wafer flow to bottleneck zone," master's thesis, Tung-Hai University, Taiwan
9 Uzsoy, R., C. Y. Lee, and L. A. Martin-Vega(1994), "A review of production planning and scheduling models in the semiconductor industry. Part II: shop-floor control," IIE Transaction, Vol. 26, No. 5, pp. 44-55
10 Spearman, M. L., David L. woodruff, and Wallace J. Hopp(1990), "CONWIP: A Pull Alternative to Kanban," International Journal of Production Research, Vol. 28, No. 5, pp. 879-894   DOI
11 Huang, C. L.(1998), "analysis on bottleneck shifting and research on its management game," master's thesis, Department of Industrial Engineering and Management, National Chiao-Tung University, Taiwan
12 Goldratt, Eliyahu M.(1990a), "The Theory of Constraints," The North River Press
13 Leachman, Robert. C. and David A. Hodges(1996), "Benchmarking semiconductor manufacturing," IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 2, pp. 158-169   DOI   ScienceOn
14 Tu, Y. M.(1998), "work-in-process management mode of wafer manufactory," master's thesis, Department of Industrial Engineering and Management, National Chiao-Tung University, Taiwan
15 Uzsoy, R., C. Y. Lee and L. A. Martin-Vega(1992), "A review of production planning and scheduling models in the semiconductor industry. Part I: system characteristics, performance evaluation and production planning," IIE Transaction, Vol. 24, No. 4, pp. 47-60   DOI   ScienceOn
16 Glassey C. R. and Resende, M. G. C.(1988a), "Closed-loop Job Release Control for VLSI Circuit Manufacturing," IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 1, pp. 36-46   DOI
17 Goldratt, Eliyahu M.(1990b), "What is the thing called theory of constraints and how should it be implemented," North River Press
18 Lu, J. J.(2004), "Release and dispatching technology of IC manufacturing oriented production plan," master's thesis, Tung-Hai University, Taiwan
19 Goldratt, Eliyahu M., Eli schragenheim, and Carol A. Ptak(2000), "Necessary but not sufficient," The North River Press
20 Lawton, J. W., Drake, A., Henderson, R., Wein, L. M., Whitney, R., and Zuanich, D.(1990), "Workload Regulating Wafer Release in a GaAs Fab Facility," IEEE Int'l Semiconductor Manufacturing Science Symposium, pp. 33-88
21 Wein, L. M.(1988), "Scheduling Semiconductor Wafer Fabrication," IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 3, pp. 115-130   DOI
22 Glassey, C. R. and M. G. C. Resende(1988b), "A Scheduling Rule for Job Release in Semiconductor Fabrication," Operations Research Letters, Vol. 7, No. 5, pp. 213-217   DOI   ScienceOn
23 Akcah, Kazunori Nemoto and Reha Uzsoy(2001), "Cycle-time improvements for photolithography process in semiconductor manufacturing," IIEEE Transactions on Semiconductor Manufacturing, Vol. 14, No. 1, pp. 48-56   DOI   ScienceOn
24 Hung, Y. F. and R. C. Leachman(1996), "A production planning methodology for semiconductor manufacturing based on interactive simulation and linear programming calculation," IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 2, pp. 257-269   DOI   ScienceOn