• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2005년도 금형가공,미세가공,플라스틱가공 공동 심포지엄
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• pp.193-197
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• 2005

This paper presents a method by which multiple holes of ultra small size can be punched simultaneously. Silicon wafers were used to fabricate punching die. Workpiece used in the present investigation were the rolled pure copper of $3{\mu}m$ in thickness and CP titanium of $1.5{\mu}m$ in thickness. The metal foils were punched with the dies and arrays of circular and rectangular holes were made. The diameter of holes ranges from $2-10{\mu}m$. The process set-up is similar to that of the flexible rubber pad forming or Guerin process. Arrays of holes were punched successfully in one step forming. The punched holes were examined in terms of their dimensions, surface qualities, and potential defect. The effects of the die hole dimension on ultra small size hole formation of the thin foil were discussed. The optimum process condition such as proper die shape and diameter-thickness ratio (d/t) were also discussed. The results in this paper show that the present method can be successfully applied to the fabrication of ultra small size hole array in a one step operation.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2010년도 춘계학술발표논문집 2부
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• pp.981-984
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• 2010

생산성 증가 및 비용 절감을 위해 반도체 공정 기술을 단순화 시키는 것이 필요하다. WBL(Wafer Backside Lamination) 기술을 이용해 필름(film) 형태로 얇은 다이접착제를 웨이퍼(wafer)에 접착하여 반도체 칩과 PCB를 붙이는 방법과 직접 PCB에 다이접착제를 붙이는 방법을 사용하면 획기적으로 공정을 단순화 시킬 수 있다. 하지만 Lamination 기법은 고온을 이용하여 모듈화된 PCB에 접착하므로 전도와 복사에 의해 주변 접착제 필름이 녹아 버리는 문제점이 발생한다. 본 연구에서는 고온으로 인한 필름 융해 현상을 방지하기 위하여 배크라이트를 설치하였으며 CFD 해석을 통해 PCB와 반도체 칩을 접착시킬 때 열이 PCB에 미치는 영향을 살펴보았다.

• Design & Manufacturing
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• 제14권4호
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• pp.58-64
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• 2020

Lately, the development of the semiconductor industry has led to the miniaturization of electronic devices. Therefore, semiconductor wafers of very thin thickness that can be used in Multi-Chip Packages are required. There is active research on the backgrinding process to reduce the thickness of the wafer. The backgrinding process polishes the backside of the wafer, reducing the thickness of the wafer to tens of ㎛. The equipment that performs the backgrinding process requires ultra-precision. Currently, there is no full auto backgrinding equipment in Korea. Therefore, in this study, ultra-precision backgrinding equipment was designed. In addition, finite element analysis was conducted to verify the equipment design validity. The deflection and structural stability of the backgrinding equipment were analyzed using finite element analysis.

• Design & Manufacturing
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• 제18권2호
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• pp.9-16
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• 2024

Recently, there has been extensive research conducted on the miniaturization of semiconductors and the improvement of their integration to achieve high-quality and high-performance electronic devices. To integrate and miniaturize multiple semiconductors, thin and precise wafers are essential. The backgrinding process, which involves high-precision processing, is necessary to achieve this. The backgrinding system is used to grind and polish the back side of the wafer to reduce its thickness to ㎛ units. This enables the high integration and miniaturization of semiconductors and a flattening process to allow for detailed circuit design, ultimately leading to the production of IC chips. As the backgrinding system performs precision processing at the ㎛ unit, it is crucial to determine the stability of the equipment's rigidity. Additionally, the flatness and surface roughness of the processed wafer must be checked to confirm the processability of the backgrinding system. IIn this paper, the goal is to verify the processability of the back grinding system by analyzing the natural frequency and resonance frequency of the equipment through computer simulation and measuring and analyzing the flatness and surface roughness of wafers processed with backgrinding system. It was confirmed whether processing damage occurred due to vibration during the backgrinding process.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.23-34
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• 2005

Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.195-201
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• 2000

Current Status: Good Electrical performance for high speed device, Solder joint reliability-Passed 1600 cycles for 4M SRAM(3.27mm DNP),-Passed 400 cycles for large die(5.71 mm DNP), Future Plan: Improving Board Level Reliability for large die size, Lead free solder evaluation.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권7호
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• pp.351-363
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• 2001

This paper presents an experimental investigation on the heat trensfer characteristic of micro pipe (MHP) array with 38 triangular microgrooves. A heat pipe is an effective heat exchanger operating without external power. The heat pipe transfers heat by means of the latent heat of vaporization and two-phase fluid flow driven by the capillary force. The overall size of the MHP array can be put undermeath a microelectonic die and integrated into the electrronic package of a microelectronin device to dissipate the heat from the die. The MHP array is fabricated by micromachining with a silicon wafer and a glass substrate. The MHP was filled with water and sealed. The experimental results show the temperature decrease of 12.1$^{\circ}C$ at the evaporator section for the input power of 5.9 W and the improvement of 28% in the heat transfer rate.

• Design & Manufacturing
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• 제10권1호
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• pp.1-6
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• 2016

In this study, the modification structure design of insulation displacement connector developed was considered for simplification of assembly process. The modified connector consisted terminal, wafer and fitting nails. The separation behavior under locking condition for pitch 1.25mm wire to board connector was measured and the apparatus for the test was made. The maximum restraining force was measured about 4.5kgf that was bigger value than the specification limit. And the pulling force of a wire was also indicated about 2.3kgf.

• 한국재료학회지
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• 제19권5호
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• pp.288-292
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• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

• Design & Manufacturing
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• 제10권1호
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• pp.19-25
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• 2016

Connectors are very important components that transmit electric signals to different parts. It must maintain intensity of the connector to prevent defects from impact and maintain contact to transmit electric signals. Most of the external parts of the connector, which act as the main framework, are formed by injection molding. However, bend deformation occurs for injection molded products due to the residual stress left inside the product after product molding. When the bend deformation is large, it does not come into complete contact when being assembled with other parts, which leads to connector contact intensity not being properly maintained. In result, the main role of the connector, which is to transmit electric signals, cannot be performed. In order to address this problem, this study conducted bend deformation cause analysis through bend deformation analysis to predict and prevent bend deformation of housings and wafers, which are injection molded products of pressure welded connectors that are normally applied in compact mobile and display products. Bend deformation analysis was carried out by checking the charging time, pressure distribution and temperature distribution through wire to board connector wafer and housing injection molding analysis. Based on the results of the bend deformation analysis results, the cause of the bend deformation was analyzed through deformation resulting from disproportional cooling, deformation resulting from disproportional contraction, and deformation resulting from ingredient orientation. In result, it was judged that the effects for bend deformation were biggest due to disproportional contraction for both the pressure welded connector wafer and housing.