• 반도체디스플레이기술학회지
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• 제16권1호
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• pp.29-33
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• 2017

This paper presents a development of vision aligner with three channels for the wafer and plate bonding machine in manufacturing of LED. The developed vision aligner consists of three cameras and performs wafer alignment of rotation and translation, flipped wafer detection, and UV Tape detection on the target wafer and plate. Normally the process step of wafer bonding is not defined by standards in semiconductor's manufacturing which steps are used depends on the wafer types so, a lot of processing steps has many unexpected problems by the workers and environment of manufacturing such as the above mentioned. For the mass production, the machine operation related to production time and worker's safety so the operation process should be operated at one time with considering of unexpected problem. The developed system solved the 4 kinds of unexpected problems and it will apply on the massproduction environment.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.981-986
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• 1993

A fast algorithm based upon geometry to measure the wafer center and the position of a wafer fiducial mark is developed and implemented on a single-axis aligner. Design issues for a controller when a National Semiconductor's LM629 is used as a PID controller of an aligner are discussed. Performance of an aligner with the algorithm and a LM629 was measured in experiments. The result shows that it takes about 4.1 seconds on average to align a hot wafer supported by metal pins on the chuck.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2553-2556
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• 2003

In the semiconductor equipment industry, the SECS/GEM protocol has been recognized as the communication standard, but in our 300mm wafer aligner being developed, this capability has not been equipped yet. In this study, we present the realization of SECS-I, SECS-II and HSMS communication protocol between factory host computer and wafer aligner. Its validity is shown in actual test environment.

• 제어로봇시스템학회논문지
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• 제8권9호
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• pp.812-817
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• 2002

This paper presents a development of high accuracy aligner and describes a method to find the orientation of a substantially circular disk shaped wafer with at least one flat region on an edge thereof. In the developed system, the wafer is spun one 360 degree turn on a chuck and the edge position is measured by a linear array to obtain a set of data points at various wafer orientation. The rotation axis may differ from wafer center by an unknown eccentricity. The flat angle is found by fitting a cosine curve to the actual data to obtain a deviation. The maximum deviation is then corrected for errors due to a finite number of data points and wafer eccentricity by calculating an adjustment angle from data points on the wafer fiat. After determining the flat angle the wafer is spun to the desired orientation. The wafer eccentricity can be calculated from four of the data points located away from the flat edge region. and the wafer is then centered.

• 반도체디스플레이기술학회지
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• 제9권3호
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• pp.47-51
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• 2010

This paper presents a wafer pre-alignment system which is improved using the image of the entire wafer area. In the previous method, image acquisition for wafer takes about 80% of total pre-alignment time. The proposed system uses only one image of entire wafer area via a high-resolution CMOS camera, and so image acquisition accounts for nearly 1% of total process time. The larger FOV(field of view) to use the image of the entire wafer area worsen camera lens distortion. A camera calibration using high order polynomials is used for accurate lens distortion correction. And template matching is used to find a correct notch's position. The performance of the proposed system was demonstrated by experiments of wafer center alignment and notch alignment.

• 반도체디스플레이기술학회지
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• 제9권1호
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• pp.11-16
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• 2010

Wafer Pre-Alignment is to find the center and the orientation of a wafer and to move the wafer to the desired position and orientation. In this paper, an area camera based pre-aligning method is presented that captures 8 wafer images regularly during 360 degrees rotation. From the images, wafer edge positions are extracted and used to estimate the wafer's center and orientation using least squares circle fitting. These data are utilized for the proper alignment of the wafer. For accurate alignments, camera calibration methods using high order polynomials are used for converting pixel coordinates into real-world coordinates. A complete pre-alignment system was constructed using mechanical and optical components and tested. Experimental results show that alignment of wafer center and orientation can be done with the standard deviation of 0.002 mm and 0.028 degree, respectively.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 추계학술대회
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• pp.410-413
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• 2009

웨이퍼 Pre-Alignment는 반도체 공정에서 장비에 웨이퍼를 놓기 전에 웨이퍼의 중심 및 방향을 정확하게 정렬할 필요가 있는데, 이를 위해서 일정한 수준 이하로 중심과 방향을 찾아 Alignment 하는 방법을 말한다. 본 논문에서는 웨이퍼를 Alignment 하기 위해 기존의 Mechanical한 방법이 아닌 Area 카메라를 통한 비접촉식 방법을 이용하였다. 이 방법은 웨이퍼를 45도씩 8번씩, 한 바퀴를 회전하여 이미지를 획득한 뒤, 이미지의 웨이퍼의 에지값 들을 이용하여 Least Square Circle Fitting을 이용하여 웨이퍼의 중심과 방향을 정확하게 측정하여 Alignment를 한다.

• 한국항행학회논문지
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• 제13권3호
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• pp.412-418
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• 2009

본 논문에서는 노치형 웨이퍼 20~25개를 일련번호가 같은 위치에 자동으로 정렬이 되도록 하여 반도체 공정 전, 후 감지기에 의해 웨이퍼의 공정상태 파악을 용이하게 하는 시스템 개발 및 정확하게 노치를 정렬하는 보정 알고리즘, 스테핑 모터 제어 알고리즘을 제안하였다. 웨이퍼 회전 시 표면 재질이 적당한 마찰 계수를 가지며 웨이퍼의 회전으로 파티클(Particle)이 발생하지 않는 소재를 사용하여 발생을 최소화 시킬 수 있었다. 또한 미끄럼 방지를 위한 기구설계 기술을 개발하였고, 수학적 검증을 통한 성능평가를 실시하였다. 본 연구 개발 시스템은 반도체 공정 진행 중 웨이퍼의 오염 방지로 반도체 수율을 향상 시킬 수 있으며, 향후 450mm 이상의 대형 웨이퍼 생성 시에도 탄력적으로 적용 할 수 있다.

• 한국재료학회지
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• 제12권2호
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• pp.117-120
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• 2002

We investigated the possibility of direct bonding of the Si ∥SiO$_2$/Si$_3$N$_4$∥Si wafers for Oxide-Nitride-Oxide(ONO) gate oxide applications. 10cm-diameter 2000$\AA$-thick thermal oxide/Si(100) and 500$\AA$-Si$_3$N$_4$LPCVD/Si (100) wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were premated wish facing the mirror planes by a specially designed aligner in class-100 clean room immediately. Premated wafer pairs were annealed by an electric furnace at the temperatures of 400, 600, 800, 1000, and 120$0^{\circ}C$ for 2hours, respectively. Direct bonded wafer pairs were characterized the bond area with a infrared(IR) analyzer, and measured the bonding interface energy by a razor blade crack opening method. We confirmed that the bond interface energy became 2,344mJ/$\m^2$ when annealing temperature reached 100$0^{\circ}C$, which were comparable with the interface energy of homeogenous wafer pairs of Si/Si.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.366-369
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• 2003

The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.