• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.781-788
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• 2011

This paper proposes a boost-input self-driven active clamp ZVS converter eliminating the extra dirve circuit for the active clamp switch. The converter used the auxiliary winding of the transformer to drive the active clamp switch and to achieve asymmetrical duty control. This paper presents the operation principle and the analyzed results of dynamic characteristics including steady state characteristics of the converter proposed. The experimental results were used to verify the theoretical predictions. A 300W (15V/20A) prototype converter that only exhibited 2-turn winding number in the auxiliary winding was sufficient to drive the active clamp switch on the input voltage of 80V. Finally, the maximum efficiency of 91.2% was achieved for the prototype converter and the proposed converter had stable closed loop characteristic with phase margin $55^{\circ}$.

• Journal of Power Electronics
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• v.2 no.3
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• pp.199-205
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• 2002

This paper compares three kinds of soft-switching circuits from viewpoints of surge suppression, load characteristic, and power efficiency for a tapped-inductor buck converter with low voltage and high current. As a result, these soft-switching techniques have achieved much higher efficiency of 80 % when compared with a hard-switching buck converter for the output condition of 1V and 20A.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.301-303
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• 2001

This paper proposes the boost input type active clamp DC-DC converter featuring the high efficiency and improved EMI characteristics. The main characteristic of the converter is to operate with the non-pulsating input and output currents. Besides, it has the zero-voltage switching (ZVS) and low voltage stress characteristics. For the proposed converter, the detailed operation principles and the simulation results are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.403-404
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• 2014

전기 자동차 및 하이브리드 자동차는 차량의 12V 부하에 전원을 공급하고 12V 배터리를 충전시키기 위해 DC/DC 컨버터를 사용한다. 이 DC/DC컨버터를 LDC(Low voltage DC/DC Converter)라 한다. 본 논문에서는 Active Clamp 방식의 포워드 컨버터를 이용하여 소용량 LDC를 개발한 내용을 소개 하였다.

• The Korean Journal of Physiology
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• v.25 no.2
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• pp.125-131
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• 1991

Inactivation properties of Ca current in the unfertilized eggs of mouse were studied by using the whole cell voltage clamp technique and single microelectrode voltage clamp technique. Membrane potential was held at -80 mV and step depolarization was applied from -50 mV to 50 mV for $200{\sim}500\;ms$. Peak of inward Ca currents was $-2{\sim}-4\;nA$ at a membrane Potentials from -20 mV to 0 mV and outward currents were not observed within the membrane voltage range studied $(-50{\sim}50\;mV)$. Inward currents were fully inactivated within 200 ms after the onset of step depolarization. As the membrane became depolarized, time constant of inactivation (${\tau}$) was decreased but remained around $20{\sim}30\;ms$ beyond 10 mV. When $Ca^{2+}$ was used as a charge earlier, inactivation of inward $Ca^{2+}$ current also occured and time course of inactivation was similar to that of $Ca^{2+}$ currents as charge carrier. In the bathing solution containing high potassium $(131\;mM\;K^+)$, process of inactivation was not changed except a parallel decrease of value for the entire range of membrane potential. Steady-state inactivation of the $current(h_{\infty})$ obtained from the double pulse experiment showed the voltage-dependent change. These results suggested that inactivation of Ca currents in the unfertilized eggs of mouse was voltage-dependent.

• Journal of IKEEE
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• v.18 no.1
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• pp.25-30
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• 2014

In this paper, SCR(Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. In order to improve latch-up immunity caused by low holding voltage of the conventional SCR, it is modified by inserting n+ floating region and n-well, and extending p+ cathode region in the p-well. The resulting ESD capability of our proposed ESD protection circuit reveals a high latch-up immunity due to the high holding voltage. It is verified that electrical characteristics of proposed ESD protection circuit by Synopsys TCAD simulation tool. According to the simulation results, the holding voltage is increased from 4.61 V to 8.75 V while trigger voltage is increased form 27.3 V to 32.71 V, respectively. Compared with the conventional SCR, the proposed ESD protection circuit has the high holding voltage with the same triggering voltage characteristic.

• Proceedings of the KIEE Conference
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• 1996.07a
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• pp.453-457
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• 1996

DC/DC converter is widely used in computer, electronic communication and industrial apparatus where the regulated dc supply is needed. FB-ZVS converter is suitable for high-power, high-frequency and constant frequency control. Because the voltage stress of the diode rectifier is high due to the ring effect, the clamp circuit is essential to reduce the voltage stress. The nondissipative active clamp circuit eliminates ring effect. Analysis of FB-ZVS converter and the validity of the active clamp circuit are studied through the simulation, and the experimental results show the superior characterics of the proposed system.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1309_1310
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• 2009

The topology of active clamp forward converter provides ZVS characteristic and also the stress of voltage and current is smaller than that of the conventional forward converters. The benefits of this technique include a higher efficiency at a high switching frequency, lower EMI/RFI. In this paper, the active clamp forward converter is designed for operation in wide range voltage and has 19.5V/120W ratings with efficiency more than 90%.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1005-1008
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• 2001

This paper presents average current-mode control AC/DC ZVT(Zero Voltage Transition) Boost Converter. This boost converter perceives feed forward signal of input and feedback signal of output for average current-mode control proposed converter employs active-clamp method for ZVT. This converter gives the good PFC(Power Factor Correction), low line current hormonic distortions and tight output voltage regulations. This converter also has a high efficiency by active-clamp method. The principle of operation, feature, and design considerations are illustrated and verified through the experiment with a 150W, 120kHz prototype converter.