• 전기학회논문지
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• 제63권11호
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• pp.1622-1625
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• 2014

The main measurement uncertainty factors in DC high-voltage dividers for a national high-voltage standard are the measurement uncertainty of low-voltage arm and the stability of a high-voltage supply. In this study, the uncertainties by the two factors are greatly improved. As a result the measurement uncertainty for the DC high-voltage divider is reduced from $16{\times}10^{-6}(k=2)$ to $8{\times}10^{-6}(k=2)$ which is at international level.

• 한국정밀공학회지
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• 제29권11호
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• pp.1174-1177
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• 2012

In voltage measurement by using voltage divider with series resistors, error is generated caused by the variation of resistance. In order to reduce these errors, the hardware cost tends to increase in the previous works. In the proposed method, three resistors are used for the voltage divider of which the organization is adjusted by using switches. Three voltages are measured and the ratio of resistance is calculated based on the measured voltages. Since the resistance ratio is calculated by measuring voltages and additional hardware cost is minimal, the voltage can be measured with high accuracy and low cost. Experimental results show that the mean absolute error is 12.1 mV when the input voltage ranges from 5 V to 50 V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.279-282
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• 1999

Frequency divider selects the channel of the frequency synthesizer. General programmable divider has many flip-flops to realize all integer division value and stability problem by using dual modules prescaler. In this paper, a new architecture of programmable divider is proposed and designed to improve these problems. The proposed programmable divider has only thirteen flip-flops. The programmable divider is designed by 0.65${\mu}{\textrm}{m}$ CMOS technology and HSPICE. Operating frequency of the programmable divider is 200MHz with a 3V supply voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1633-1635
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• 1994

This paper presents the development technology of standard resistor divider for full lightning impulse voltage. The ability of high voltage bulk power equipment to withstand lighting stroke is usually evaluated by means of full lightning impulse voltage. Lightning impulse voltage test has been essential to evaluate the insulation performance of electrical power apparatus. Recently International standard (IEC 60) on high voltage measurement techniques is being revised and requests a formal traceability of high voltage measurements. Therefore, general interest for this area has grown considerably during last years, and several international intercomparisions have been completed already worldwide, i.e. Europe, Japan, America etc.. In this viewpoint, we have also investigated the standard resistor divider with shield, which satisfies the IEC recommendation.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2010년도 한국컴퓨터종합학술대회논문집 Vol.37 No.1(C)
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• pp.221-225
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• 2010

본 연구에서는 제한된 온도 영역에서 보통 정밀 온도 측정 소자로 많이 쓰이는 NTC 써미스터를 사용하여 전압 분배 회로(voltage divider circuits)를 구성하였다. 분압 저항이 온도측정 해상도에 미치는 영향을 분석하고, 회로의 분압 저항을 결정하는 방법으로서 측정하고자 하는 온도 구간의 최대 온도와 최저 온도의 NTC 써미스터 저항 값을 조화평균을 사용하여 분압 저항(divider resistance)으로 사용하였다. 선택한 분압 저항이 이상적인 저항인지에 대하여 조화평균으로 계산한 분압 저항과 대조군 저항으로 전압 분배 회로를 병렬로 구성하였다. 센서들을 항온조 넣어 설정온도($50^{\circ}C$, $70^{\circ}C$, $90^{\circ}C$)에서 각각의 온도를 측정한 후 측정 데이터의 표준편차를 구하여 평균 온도 분해능을 비교 하는 실험을 하였다. 실험결과 측정온도 구간의 최대 온도와 최소 온도에서의 NTC 써미스터 저항 값을 조화평균으로 계산한 분압 저항 값이 대조군 저항에 비해 설정온도에서 보다 높은 평균 온도 분해능(sensing resolution)을 보였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.1037-1038
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• 2011

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1530-1533
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• 2005

Total 12 units of high power klystron-modulator systems as microwave source is under operation for 2.5-GeV electron linear accelerator in Pohang Light Source(PLS) linac. RF power and beam power of klystron are precisely measured for the effective control of electron beam. A precise measurement and measurement equipment with good response characteristics are required for this. Input power of klystron is calculated from the applied voltage and the current on its cathode. Tiny measurement error severely effects RF output power value of klystron. Therefore, special care is needed to measure precise beam voltage. Capacitive voltage divider(CVD) unit is intended for the measurement of beam voltage of 400 kV generated from the pulsed klystron-modulator system. Main parameter to determine the standard capacitance in the high arm of CVD is dielectric constant of insulation oil. Therefore CVD should be designed to have a minimum capacitance variation due to voltage, frequency and temperature in the measurement range. This paper will discuss the analysis of capacitive voltage divider for a pulsed high-voltage measurement, and the empirical relations between capacitance and oil temperature variation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 A
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• pp.284-286
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• 1999

The 7-dial inductive voltage divider (IVD) which is divided the in put voltage precisely upto 10-7 were fabricated by using the toroidal cores made of super-mumetal strips of 0.025 mm thick and special decade switches. The cores ate of the initial permeability of 200,000 and magnetic flux density of 0.5 T. The in phase and quadrature ratio errors are evaluated to less than ${\pm}4{\times}10^{-7}$ and ${\pm}5{\times}10^{-6}$ rad. respectively. The fabrication techniques used are more discussed in this paper.

• 한국통신학회논문지
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• 제27권6C호
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• pp.619-624
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• 2002

본 논문에서는 50%의 duty cycle 출력을 가지며, 디지털 방식으로 분주수를 제어할 수 있는 새로운 분주기 구조를 제안하였다. 그리고 0.25$\mu\textrm{m}$ 2-poly, 5-metal CMOS 공정 파라미터를 이용한 HSPICE 모의실험을 통해서 제안한 주파수 분주기를 이용한 900MHz 주파수 합성기를 설계하였다. 제안한 주파수 분주기의 동작은 0.657m 2-poly, 2-metal CMOS 공정을 사용하여 제작한 칩을 측정하여 확인하였다. 설계한 전압제어발진기(VCO)는 2.5V 전원전압 하에서 900Mh의 충간주파수, $\pm$10%의 동작 범위, 154MHz/V의 이득을 가진다. 또한 모의실험 결과 주파수 합성기의 settling time은 약 $1.5\mu\textrm{m}$이고 짝수와 홀수 분주시 50%의 duty cycle과 820MHz~1GHz의 동작 주파수 범위를 갖으며, 전력소모는 대략 70mW 임을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.