• The Transactions of the Korean Institute of Power Electronics
• /
• v.23 no.3
• /
• pp.153-160
• /
• 2018

Recent trends in high-power-density applications have highlighted the importance of designing power converters with high-frequency operation. However, conventional LLC resonant converters present limitations in terms of high-frequency driving due to switching losses during the turn-off period. Switching losses are caused by the overlap of the voltage and current during this period, and can be decreased by reducing the switch voltage. In turn, the switch voltage can be reduced through a series connection of four switches, and additional circuitry is essential for balancing the voltage of each switch. In this work, a three-level LLC resonant converter that can operate at high frequency is proposed by reducing switch losses and balancing the voltages of all switches with only one capacitor. The voltage-balancing principle of the proposed circuit can be extended to n-level converters, which further reduces the switch voltage stress. As a result, the proposed circuit is applicable to high-input applications. To confirm the validity of the proposed circuit, theoretical analysis and experimental verification results from a 350 W-rated prototype are presented.

• Journal of Electrical Engineering and Technology
• /
• v.12 no.3
• /
• pp.1203-1210
• /
• 2017

Switched-inductor (SL) Z-source three-level inverter is a novel high power topology. The SL based impedance network can boost the input dc voltage to a higher value than the single LC impedance network. However, as all the neutral-point-clamped (NPC) inverters, the SL Z-source three-level inverter has to balance the neutral-point (NP) potential too. The principle of the inverter is introduced and then the effects of NP potential unbalance are analyzed. A NP balancing method is proposed. Other than the methods for conventional NPC inverter without Z-source impedance network, the upper and lower shoot-through durations are corrected by the feedforward compensation factors. With the proposed method, the NP potential is balanced and the voltage boosting ability of the Z-source network is not affected obviously. Simulations are conducted to verify the proposed method.

• Journal of the Korean Society of Industry Convergence
• /
• v.25 no.3
• /
• pp.451-459
• /
• 2022

Recently, in accordance with the demand for a large capacity of a secondary battery according to an increase in the demand for energy storage devices, a modular series battery configuration is essential. Accordingly, various cell balancing techniques have been proposed to prevent high efficiency and performance degradation of the battery. In this paper, propose a battery voltage balancing topology consisting of a flyback DC/DC converter type of a SIMO (Single-Input-Multiple Output) two-switch configuration for a series battery configuration. The proposed topology shows a structure in which a DC/DC converter connected to each module and a battery cell share one transformer. The topology cell balancing operation is a principle in which the voltage balancing converter of the battery converges to the same value through a transformer that shares a magnetic flux with the cells constituting the module through a single high-frequency transformer. In this paper, the dynamic characteristics analysis of the proposed circuit using PSIM was based and it was verified through experiments on one module.

• Proceedings of the KIEE Conference
• /
• 1994.07a
• /
• pp.373-375
• /
• 1994

In realizing a three-level GTO inverter, we should keep the voltage balancing of DC-link capacitors and consider minimum on/off time of GTO thyristors in order to make the same blocking voltage across each device and to minimize the harmonic components of the output voltage and current. In this raper, a new PWM scheme based on space voltage vectors, by which it is possible to keep neutral-point voltage and avoid narrow pulse, is presented. Experimental results verify that the proposed PWM control scheme is suitable fur hish power and high voltage three-level GTO inverters applied to induction motor drives.

• Journal of Power Electronics
• /
• v.16 no.6
• /
• pp.2099-2108
• /
• 2016

The cascaded multilevel converter is widely adopted to medium/high voltage and high power electronic applications due to the small harmonic components of the output voltage and the facilitation of modularity. In this paper, the operation principle of a T-type H-bridge topology is investigated in detail, and a carrier phase shifted pulse width modulation (CPS-PWM) based control method is proposed for this topology. Taking a virtual five-level waveform achieved by a unipolar double frequency CPS-PWM as the output object, PWM signals of the T-type H-bridge can be obtained by reverse derivation according to its switching modes. In addition, a control method for the T-type H-bridge based cascaded multilevel converter is introduced. Then a single-phase T-type H-bridge cascaded multilevel static var generator (SVG) prototype is built, and a repetitive controller based compound current control strategy is designed with the DC-link voltage balancing control scheme analyzed. Finally, simulation and experimental results validate the correctness and feasibility of the proposed modulation method and control strategy for T-type H-bridge based cascaded multilevel converters.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.20 no.4
• /
• pp.321-329
• /
• 2015

The static synchronous compensator (STATCOM) of cascaded H-bridge configuration accompanying multiple separate DC sides is inherently subject to the problem of uneven DC voltages. These DC voltages in one leg can be controlled by adjusting the AC-side output voltage of each cell inverter, which is proportional to the active power. However, when the phase current is extremely small, large AC-side voltage is required to generate the active power to balance the cell voltages. In this study, an alternative zero-sequence current injection method is proposed, which facilitates effective cell balancing controllers at no load, and has no effect on the power grid because the injected zero sequence current only flows within the STATCOM delta circuit. The performance of the proposed method is verified through simulation and experiments.

• Journal of Power Electronics
• /
• v.17 no.1
• /
• pp.115-126
• /
• 2017

This paper presents a new cascaded asymmetrical single phase multilevel converter with a reduced number of isolated DC sources and power semiconductor switches. The proposed inverter has only two H-bridges connected in cascade, one switching at a high frequency and the other switching at a low frequency. The Low Switching Frequency Inverter (LSFI) generates seven levels whereas the High Switching Frequency Inverter (HSFI) generates only two levels. This paper also presents a solution to the capacitor balancing issues of the LSFI. The proposed inverter has lot of advantages such as reductions in the number of DC sources, switching losses, power electronic devices, size and cost. The proposed inverter with a capacitor voltage balancing algorithm is simulated using MATLAB/SIMULINK. The switching logic of the proposed inverter with a capacitor voltage balancing algorithm is developed using a FPGA SPATRAN 3A DSP board. A laboratory prototype is built to validate the simulation results.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.9 no.2
• /
• pp.187-193
• /
• 2004

For a power source of usual electronic devices such as PDA, smart phone, UPS and electric vehicle, the battery made of serially connected multiple cells is generally used. In this case, if there are some unbalanced among cell voltages, the total lifetime and the total capacity of the battery are limited to a lower value. To maintain a balanced condition in cells, an effective method of regulating the cell voltage in indispensable. In this paper, we propose the design of a balancing circuit for electronic appliances. The balancing system was controlled by a micro-controller which enables to implement the balancing action during charging period. Proposed method has been verified by the experiment using the charger and recorder. The experimental results show that the individual battery equalization can improve battery capacity and battery lifetime and performance through an extended operational time.

• Proceedings of the KSME Conference
• /
• 2001.06c
• /
• pp.53-58
• /
• 2001

This paper presents a high resolution capacitive microaccelerometer for applications to personal information systems. We reduce the mechanical noise level of the microaccelerometer by increasing the proof-mass based on deep RIE process. We reduce the electrical noise level by increasing the amplitude of an AC sense voltage. The high sense voltage is obtained by DC-to-DC voltage multiplier. In order to solve the nonlinearity problem caused by the high sense voltage, we modify the conventional comb electrode of straight finger type into that of branched finger type, resulting in self force-balancing effects for enhanced detection linearity. The proposed branched finger capacitive microaccelerometer was fabricated by the deep RIE process of an SOI wafer. The fabricated microaccelerometer reduces the electrical noise at the level of $2.4{\mu}g/\sqrt{Hz}$ for the sense voltage of l6.5V, which is 10.1 times smaller than the electrical noise level of $24.3{\mu}g/\sqrt{Hz}$ at 0.9V. For the sense voltage higher than 2V, the electrical noise level of the microaccelerometer became smaller than the constant mechanical noise level of $11{\mu}g/\sqrt{Hz}$. Total noise level, including the electrical noise and the mechanical noise, has been measured as $9{\mu}g/\sqrt{Hz}$ for the sense voltage of 16.5V, which is 3.2 times smaller than the total noise of $28.6{\mu}g/\sqrt{Hz}$ for the sense voltage of 0.9V. The self force-balancing effect results in the increased stiffness of 1.98 N/m at the sense voltage of 17.8V, compared to the stiffness of 1.35 N/m at 0V, thereby generating the additional stiffness at the rate of $0.002N/m/V^{2}$.

• Proceedings of the KIPE Conference
• /
• 2011.11a
• /
• pp.26-27
• /
• 2011

This paper focuses on the zero-voltage/zero current transition voltage equalization circuit for the series connected battery cell. By adding auxiliary resonant cells at the main switching devices such as MOSFET or IGBT, zero current switching is achieved and turned off loss of switching elements is eliminated and by the voltage/second balancing of the inductor, zero voltage switching can be applied to switching element. Transformer coupling between battery cells and ZVZCT (Zero Voltage Zero Current Transition) switching method allow the fast balancing speed and high frequency operation, which reduces the size and weight of the circuit. The validity of the battery equalization is further verified using simulation involving four lithium-ion battery cell models.