• The Research Journal of the Costume Culture
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• v.30 no.1
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• pp.66-87
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• 2022

This study explores the possibility of creating new experimental hanbok designs by accommodating the latest world fashion trends and the changing needs of consumers, in order to attempt to overcome the limitations of traditional Korean fashion design. To do so, We analyze works by contemporary Korean fashion designers to investigate current developments in Korean fashion design and to identify areas of improvement within hanbok design. The results show that most contemporary hanbok designs repeat stereotypes of traditional hanbok with minor modifications. So there arises a need to create new hanbok designs that are clearly distinct from traditional hanbok but also maintain its core features. To develop such designs, I apply the techniques of deconstruction fashion, which allow making experiments with form, composition, and materials use to realize new aesthetics. The use of CLO 3D fashion design software also proves to be very efficient for developing experimental designs. The study results make meaningful contributions to the development of virtual clothing and 3D fashion for hanbok, particularly as metaBUS, a cloud-based research synthesis platform, is rapidly gaining ground, and reality and virtual reality are increasingly mixed in everyday life. This attempt at 3D design of hanbok is expected to trigger more creative experimentation in hanbok design.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1177-1180
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• 2005

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1997.10a
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• pp.212-215
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• 1997

이동통신 시스템에서 고속 데이터, 그래픽, 동화상 등과 같은 이동 멀티미디어 서비스를 추가로 제공하기 위해서는 기존의 음성 및 데이터 뿐만 아니라 화상, 영상 데이터를 고속으로 교환할수 있도록 시스템 내부 프로세서간 메시지 교환을 위한 CDMA 상호연결 통신망에 대한 성능 향상이 요구된다. 본 논문에서는 CDMA 상호연결망의 성능 향상을 위한 가상 토큰 이중버스(VTDB:Virtual Token Dual Bus)의 구조 및 매체접근제어 프로토콜을 제안하고 성능을 평가하였다. 제안하는 VTDB 프로토콜에서는 공유버스에 대한 매체접근 제어시 가상 토큰에 의한 예약 기능을 사용하여 전송할 메시지를 가진 노드간 가상토큰 전달시간(스위치오버 시간)을 줄여 버스의 성능을 향상시키며, 또한 각 노드를 독립된 두 개의 버스에 동시에 연결하여 메시지 전송시 두 버스를 함께 사용하게 함으로써 통신망의 성능 및 신뢰성을 개선한다. 해석적 방법을 이용한 성능 분석을 통하여 본 논문에서 제안한 VTDB 프로토콜의 성능이, 기존의 단일버스 구조를 갖는 가상토큰 전달방식의 매체접근 제어 프로토콜과 비교하여 우수함을 확인할수 있었다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1137-1138
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• 2008

The purpose of this study is to implement a landscape lighting system that displays full color video by precisely controlling the R, G, B (Red, Green, Blue) LEDs which have a resolution of 256 each. The system implemented in this study consists of a PC, MASTER, SLAVEs and MODULEs. The PC sets the various landscape lighting displays, and the image files can be sent to the MASTER through a virtual serial port connected to the USB (Universal Serial Bus). The MASTER sends a sync signal to the SLAVE. The SLAVE uses the signal received from the MASTER and the landscape lighting display pattern.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.951-954
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• 2002

This paper presents the implementation of hash functions for IPSEC chip. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as VPNs (virtual private networks). Because diverse algorithms are used in Internet, various hash algorithms are required for IPSec chip. Therefore, we implemented SHA-1, HAS-160 and MD5 in one chip. These hash algorithms are designed to reduce the number of gates. SHA-1 module is combined with HAS-160 module. As the result, the required logic elements are reduced by 27%. These hash algorithms have been implemented using Altera's EP20K1000EBC652-3 with PCI bus interface.

• Journal of the Korean Society of Industry Convergence
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• v.18 no.3
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• pp.150-156
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• 2015

In this paper, it was proposed a new technology to improve the performance of the remote control in virtual reality applications. The operator must know the information of surroundings of the robot, collision possibility of the equipment, and force feedback of the manipulator. The time delay problem occurs in the tele-operating and it causes vibration and expressive power of the manipulator owing to bidirectional force feedback. We presented a new control method to control of the teleoperating system based on serial bus. The reliability is evaluated by simulation.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.127-129
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• 2002

NP Forum에서는 다양한 밴더의 네트워크 프로세서와 스위치 패브릭간에 물리적 인터페이스를 제공하기 위해 CSIX-L1(Common Switch Interface-Level 1 )인터페이스를 표준화하였다. IBM 네트워크 프로세서는 MPLS 및 VPN, VLAN, Security, Ipv6와 같은 다양한 어플리케이션과 TBI. SMII CMII. POS bus등 다양한 가입자 인터페이스를 지원하며, L2 기 반에서 2.5Gbps 이상의 패킷 처리를 수행하기 때문에 많은 시스템에 사용된다. 그러나 IBM네트워크 프로세서는 스위치 인터페이스로 DASL인터페이스를 사용한다. 따라서 DASL인 터페이스와 CSIX-L1 인터페이스를 정합하기 위해서는 IBM UDASL칩을 이용해 DASL인 터페이스를 UTOPIA-L3인터페이스로 변환해야 하며, 이것을 다시 CSIX-L1인터페이스로 변환해야 한다. 따라서 본 논문에서는 UTOPIA-L3인터페이스 패킷과 CSIX-L1인터페이스 프레임을 상호 변환하는 모듈을 설계하였으며, 32비트 데이터 버스와 최대 125MHz로클록을 사용해 최대 4Gbps의 패킷처리를 제공하도록 구현하였다. 또한 스위치 패브릭의 특정 포트에서 과잉 트래픽 전달로 인해 발생할 수 있는 블로킹을 방지하기 위해 네트워크 프로세서에게 3개의 Priority／최대 64개 포트수의 VOQ(Virtual Output Queue)를 제공하는 기법에 대해서 기술한다.

• IE interfaces
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• v.22 no.2
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• pp.185-191
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• 2009

In this study, we propose an improved group location tracking scheme (GLS) called integrated GLS (IGLS) which, in addition to the group location registration of the GLS, sends an integrated group registration message to a virtual visitor location register (VVLR) instead of sending an individual group registration message. This integrated procedure of proposed scheme leads registration cost of group registration and group location registration to be reduced significantly. Numerical results demonstrate that our proposed IGLS outperforms conventional GLS and delayed GLS (dGLS). The IGLS can be applied effectively on public transportation systems such as subway, train and bus.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.89-96
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• 2009

As increasing the number of digital control devices installed on aircrafts and their transmission speed, various digital data buses have been introduced to provide reliable and high-speed characteristics. These characteristics of avionics data bus are highly related on the fault-tolerant performance which can make minimize jitter and loss during data transfer. In this paper, we concerned about a new traffic shaping scheme for increasing the reliability of Avionics Full Duplex Switched Ethernet (AFDX) systems based on ARINC 664 standard. We note that the conventional AFDX with a single regulator per virtual link system may produce aggregated traffics as the number of virtual links increasing. The aggregated traffic results in large jitters among frames. To remedy for the jitter and loss of data, we propose a dual regulator scheme for the AFDX system. The purpose of the additional regulator is to additionally regulate aggregated traffics from a number of per virtual link regulators. Using NS-2 simulator, we show that the proposed scheme provides a better performance than the single regulator one. It is worthwhile note that the proposed AFDX with Dual Regulator scheme can be employed to not only aircraft networks but other QoS sensitive networks for robot and industrial control systems.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.244-253
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• 2000

Since no single routing-switching combination performs the best under various different types of applications, a flexible network is required to support a range of polices. This paper introduces an implementation of a look-up table routing engine offering flexible routing and switching polices without performance degradation unlike those based on microprocessors. By deciding contents of look-up tables, the engine can implement wormhole routing, virtual cut-through routing, and packet switching, as well as hybrid switching, under a variety of routing algorithms. Since the routing engine has a piplelined look-up table architecture, the routing delay is as small as one flit, and thus it can overlap multiple routing actions without performance degradation in comparison with hardwired routers dedicated to a specific policy. Because four pipeline stages do not induce a hazard, expensive forwarding logic is not required. The routing engine can accommodate four physical links with a time shared cut-through bus or single link with a cross-bar switch. It is implemented using Xilinx 4000 series FPGA.