• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.106-111
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• ETRI Journal
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• v.27 no.5
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• pp.504-510
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• 2005

This paper proposes a novel low-power video decoding scheme. In the encoded video bitstream, there is quite a large number of non-coded blocks. When the number of the non-coded blocks in a frame is known at the start of frame decoding, the workload of the video decoding can be estimated. Consequently, the supply voltage of very large-scale integration (VLSI) circuits can be lowered, and the power consumption can be reduced. In the proposed scheme, the encoder counts the number of non-coded blocks and stores this information in the frame header of the bitstream. Simulation results show that the proposed scheme reduces the power consumption to about 1/10 to 1/20.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.157-160
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• 2007

System realization and video watermarking using spatial and interframe information is presented in this paper. The system is constructed with DSP processor to process compression and watermark algorithm with real time. Video watermark algorithm is used the watermark insertion using the spatial and interframe. As a results, the processing time of D1 image per frame is 32.1msec in DSP.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.387-396
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• 2004

In this paper, we propose an algorithm that distributes processor time to the tasks decoding encoded frames with a goal maximizing total QoS (quality of services) of video conference system. An encoded frame has such a characteristic that the QoS of recovered frame image also increases as the processor time given for decoding the frame gets to increase. Thus, the quality of decoded image for each frame can be represented as a QoS function of the amount of service time given to decode. In addition, every stream of video conference has close time-dependency between continuous frames belonging to the same stream. Based on the time-dependency and QoS functions, we propose an on-line frame scheduling algorithm which does not schedule all frames in the system but just a few frames while maximizing total QoS of video streams in the conference. The simulation results show that, as the system load gets to increase, the proposed algorithm compared to the existing EDF algorithm can reduce the quality of decoded frame images more smoothly and show the movements of conference attendees more naturally without short cutting.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.65 no.4
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• pp.326-334
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• 2016

In this paper for developing and implementing the realtime HD level video streaming transmitter which is operated on the multi-platform in all network and client environment compared to the exist video live streaming transmitter. We design the realtime HD level video streaming transmitter supporting the multi-platform using the TMS320DM386 video processor of T.I company and then porting the Linux kernel 2.6.29 and implementing the RTSP(Real Time Streaming Protocol)/RTP(Real Time Transport Protocol), HLS(Http Live Streaming), RTMP(Real Time Messaging Protocol) that can support the multi-platform of video stream protocol of the received equipments (smart phone, tablet PC, notebook etc.). For proving the performance of developed video streaming transmitter, we make the testing environment for testing the performance of streaming transmitter using the notebook, iPad, android Phone, and then analysis the received video in the client displayer. In this paper, we suggest the developed the Realtime HD(High Definition) level Video Streaming transmitter performance data values higher than the exist products.

• Journal of Broadcast Engineering
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• v.9 no.4 s.25
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• pp.434-445
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• 2004

Motion Estimation is an essential module in video encoders based on international standards such as H.263 and MPEG. Many fast motion estimation algorithms have been proposed in order to reduce the computational complexity of a well-known full search algorithms(FS). However, these fast algorithms can not work efficiently in DSP processors recently developed for video processing. To solve for this. we propose an efficient motion estimation scheme optimized in the DSP processor like Philips TM1300. A motion vector predictor is pre-estimated and a small search range is chosen in the proposed scheme using strong motion vector correlation between a current macro block (MB) and its neighboring MB's to reduce computation time. An MPEG-4 SP@L3(Simple Profile at Level 3) encoding system is implemented in Philips TM1300 to verify the effectiveness of the proposed method. In that processor, we can achieve better performance using our method than other conventional ones while keeping visual quality as good as that of the FS.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.5
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• pp.216-219
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• 2006

This paper presents an XML based standard specification of remote control protocol for home appliances. In the framework level, the XML protocol provides a useful bridge between services and platforms. The proposed protocol has been implemented into a personal video recorder for remote recording service. The results imply the potential of global standards for remote control by its minimum overhead in network and processor. The proposed XML is designated RCXML in this paper.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.373-376
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• 2001

This paper has been studied a real-time video frame data processing control that used the linear systolic array for motion estimation. The proposed data control processing provides to the input data into the multiple processor array unit(MPAU) from search area and reference block data. The proposed data control architecture has based on two slice band for input data processing. And it has no required external control logic blocks for input data as like reference block or search area data.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.443-444
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• 2007

본 연구에 따른 영상 신호의 처리 방법은, 하나의 화면을 중요도에 따라 복수의 영역들로 분할하는 단계 그리고 분할된 화면들 각각에 대응하는 영상 신호를 서로 다른 프레임을 (Frame-rate)로 디코딩하는 단계를 포함한다. 상술한 영상 신호의 처리 방법에 따라 시야에서 민감한 화면만을 인코딩한 최대 화질로 재생하고 덜 민감한 화면 영역은 상대적으로 낮은 화질로 재생하여 이득을 제공할 수 있다.