• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.12
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• pp.1112-1117
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• 2006

The properties of LTCC green tape with addition of binder were investigated in order to understand an effects of binder on multilayer processing. A green sheet form was fabricated through tape casting method with the MLS-22 powder. The lamination density increased with increasing amount of binder and lamination pressure. With increasing amount of binder, the elongation of ceramic sheets increased but the tensile stress and air-permeability decreased. The addition of excessive binder is caused defects in the green sheet during via hole punching. The optimum condition of the via hole without defects was observed from amount of the binder 10 wt%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.201-201
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• 2010

볼로미터 제작 공정 중 One step via 공정 시 via hole 모양에 의해 정기적 연결 및 구조적 안정성에 문제를 해결하기 위하여 다른 via 식각 방식으로 공정을 진행하였으며 그에 따른 via 공정 차이에 대한 결과를 연구하였다.

• Laser Solutions
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• v.6 no.1
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• pp.9-16
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• 2003

Micromachining using the DPSS 3rd Harmonic Laser (355nm) has outstanding advantages as a UV source in comparison with Excimer lasers in various aspects such as maintenance cost, maskless machining, high repetition rate and so on. It also has the greater absorptivity of many materials in contrast to other IR sources. In this paper, the process for micro-drilling of blind hole in Cu/PI/Cu substrate with the DPSS UV laser and the scanning device is investigated by the experimental methods. It is known that there is a large gap between the ablation threshold of copper and that of PI. We use the Archimedes spiral path for the blind hole with different energy densities to ablate the different material. Finally, the blind via hole of diameter 100$\mu\textrm{m}$ and 50$\mu\textrm{m}$ was drilled.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.55-58
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• 2018

Low-cost and large-scale fabrication method of nanohole array, which comprises nanoscale voids separated by a few tens to a few hundreds of nanometers, has opened up new possibilities in biomolecular sensing as well as novel frontier optical devices. One of the key aspects of the nanohole array research is how to control the hole size following each specific needs of the hole structure. Here, we report the extensive study on the fine control of the hole size within the range of 500-2500 nm via surface-catalyzed chemical deposition. The initial hole structures were prepared via conventional photo-lithography, and the hole size was decreased to a designed value through the surface-catalyzed chemical reduction of the gold ion on the predefined hole surfaces, by simple dipping of the hole array device into the aqueous solution of gold chloride and hydroxylamine. The final hole size was controlled by adjusting reaction time, and the optimal experimental condition was obtained by doing a series of characterization experiments. The characterization of size-controlled hole array was systematically examined on the image results of optical microscopy, field emission scanning electron microscopy(FESEM), atomic-force microscopy(AFM), and total internal reflection microscopy.

• Journal of Information Display
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• v.12 no.1
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• pp.47-50
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• 2011

Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.1069-1070
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• 2013

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.357-358
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• 2008

• The Magazine of the IEIE
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• v.21 no.8
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• pp.39-47
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• 1994

전자제품의 소형화와 반도체 및 관련 Packaging 기술의 발달로 인해 PCB는 회로의 세선화 및 Via Hole의 소형화, 다양화 그리고 두께의 박판화의 추세로 사양이 변하고 있다. 이를 달성하기 위해 PCB 제조 Process에 변화가 있으며 또한 새로운 형태의 PCB 제조방법이 모색되고 있다. 원판에서도 박판화의 대응으로 내연성이 강조되고 있으며 고주파용으로는 저유전율, 특수 동박이 요구되고 있다. 신 PCB 제조공정 및 공법으로는 특수 Via Hole 사용, ?, ED, Direct Plate가 있다. 또한 PCB는 Packaging 기술의 하나로 이해되며 강조되고 있다.

• 전기의세계
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• v.50 no.5
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• pp.16-21
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• 2001