• Title/Summary/Keyword: Verilog-A

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Design of Variable Average Operation without the Divider for Various Image Sizes (다양한 영상크기에 적합한 나눗셈기를 사용하지 않은 가변적 평균기의 설계)

  • Yang, Jeong-Ju;Jeong, Hyo-Won;Lee, Sung-Mok;Choi, Won-Tae;Kang, Bong-Soon
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.4
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    • pp.267-273
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    • 2009
  • In this paper, we proposed a variable average operation for a WDR(Wide Dynamic Range). The previously proposed average operation [5] improves hardware efficiency and complexity by replacing divider with multiplier. However, the previously proposed method has some weak-points. For example, there are counting horizontal and vertical length, and then the multiplier selects a Mode set by the user when the lengths exactly correspond with the image's size in the Mode. To compensate some weak-points, we change a Mode selection methods as a using the image's total size. Also, we propose another feature that it can be applied to various image sizes. To get a more accurate average, we add an external compensation value. We design the variable average operation using a Verilog-HDL and confirm that the Serial Multiplier's structure is better efficiency than Split Multiplier's structure.

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Low Area Hardware Design of Efficient SAO for HEVC Encoder (HEVC 부호기를 위한 효율적인 SAO의 저면적 하드웨어 설계)

  • Cho, Hyunpyo;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.1
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    • pp.169-177
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    • 2015
  • This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

Real-Time Hardware Design of Image Quality Enhancement Algorithm using Multiple Exposure Images (다중 노출 영상을 이용한 영상의 화질 개선 알고리즘의 실시간 하드웨어 설계)

  • Lee, Seungmin;Kang, Bongsoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.11
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    • pp.1462-1467
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    • 2018
  • A number of algorithms for improving the image quality of low light images have been studied using a single image or multiple exposure images. The low light image is low in contrast and has a large amount of noise, which limits the identification of information of the subject. This paper proposes the hardware design of algorithms that improve the quality of low light image using 2 multiple exposure images taken with a dual camera. The proposed hardware structure is designed in real time processing in a way that does not use frame memory and line memory using transfer function. The proposed hardware design has been designed using Verilog and validated in Modelsim. Finally, when the proposed algorithm is implemented on FPGA using xc7z045-2ffg900 as the target board, the maximum operating frequency is 167.617MHz. When the image size is 1920x1080, the total clock cycle time is 2,076,601 and can be processed in real time at 80.7fps.

Depth Image Distortion Correction Method according to the Position and Angle of Depth Sensor and Its Hardware Implementation (거리 측정 센서의 위치와 각도에 따른 깊이 영상 왜곡 보정 방법 및 하드웨어 구현)

  • Jang, Kyounghoon;Cho, Hosang;Kim, Geun-Jun;Kang, Bongsoon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.5
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    • pp.1103-1109
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    • 2014
  • The motion recognition system has been broadly studied in digital image and video processing fields. Recently, method using th depth image is used very useful. However, recognition accuracy of depth image based method will be loss caused by size and shape of object distorted for angle of the depth sensor. Therefore, distortion correction of depth sensor is positively necessary for distinguished performance of the recognition system. In this paper, we propose a pre-processing algorithm to improve the motion recognition system. Depth data from depth sensor converted to real world, performed the corrected angle, and then inverse converted to projective world. The proposed system make progress using the OpenCV and the window program, and we test a system using the Kinect in real time. In addition, designed using Verilog-HDL and verified through the Zynq-7000 FPGA Board of Xilinx.

A SOC Design Methodology using SystemC (SystemC를 이용한 SOC 설계 방법)

  • 홍진석;김주선;배점한
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.153-156
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    • 2000
  • This paper presents a SOC design methodology using the newly-emerging SystemC. The suggested methodology firstly uses SystemC to define blocks from the previously-developed system level algorithm with internal behavior and interface being separated and validate such a described blocks' functionality when integrated. Next, the partitioning between software and hardware is considered. With software, the interface to hardware is described cycle-accurate and the other internal behavior in conventional ways. With hardware, I/O transactions are refined gradually in several abstraction levels and internal behavior described on a function basis. Once hardware and software have been completed functionally, system performance analysis is performed on the built model with assumed performance factors and influences such decisions regressively as on optimum algorithm selection, partitioning and etc. The analysis then gives constraint information when hardware description undergoes scheduling and fixed-point trans- formation with the help of automatic translation tools or manually. The methodology enables C/C++ program developers and VHDL/Verilog users to migrate quickly to a co-design & co-verification environment and is suitable for SoC development at a low cost.

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A Generator of 64~8,192-point FFT/IFFT Cores with Single-memory Architecture for OFDM-based Communication Systems (OFDM 기반 통신 시스템용 단일 메모리 구조의 64~8,192점 FFI/IFFFT 코어 생성기)

  • Yeem, Chang-Wan;Jeon, Heung-Woo;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.1
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    • pp.205-212
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    • 2010
  • This paper describes a core generator (FCore_Gen) which generates Verilog-HDL models of 640 different FFT/IFFT cores with selected parameter value for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed m $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

A Hardware Design of Effective Intra Prediction Angular Mode Decision for HEVC Encoder (HEVC 부호기를 위한 효율적인 화면내 예측 Angular 모드 결정 하드웨어 설계)

  • Park, Seungyong;Choi, Juyong;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.4
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    • pp.767-773
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    • 2017
  • In this paper, we propose a design of Intra prediction angular mode decision for HEVC encoder. Intra prediction coding of HEVC is a method for predicting a current block by referring to samples reconstructed around a current block. Intra prediction supports a total of 35 modes with 1 DC mode, 1 Planar mode, and 33 Angular modes. Intra prediction coding of HEVC works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original pixel, using an algorithm that determines angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9K and operating speed is 2GHz.

Counterattack Method against Hacked Node in CAN Bus Physical Layer (CAN 버스 물리 계층에서 해킹된 노드의 대처 기법)

  • Kang, Tae-Wook;Lee, Jong-Bae;Lee, Seongsoo
    • Journal of IKEEE
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    • v.23 no.4
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    • pp.1469-1472
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    • 2019
  • CAN bus in automotive applications does not assign node addresses. When a node is hacked and it transmits malicious data frame, it is difficult to resolve which node is hacked. However, this CAN bus internal attack seriously threatens the safety of a car, so a prompt counterattack is necessary in the CAN bus physical layer. This paper proposes a counterattack method against malicious CAN bus internal attack. When a malicious data frame is detected, an intrusion detection system in the CAN bus increases the error counter of the malicious node. Then, the malicious node is off from the bus when its error counter exceeds its limit. A CAN controller with the proposed method is implemented in Verilog HDL, and the proposed method is proved to counterattack against malicious CAN bus internal attack.

Hardware implementation of automated haze removal method capable of real-time processing based on Hazy Particle Map (Hazy Particle Map 기반 실시간 처리 가능한 자동화 안개 제거방법의 하드웨어 구현)

  • Sim, Hwi-Bo;Kang, Bong-Soon
    • Journal of IKEEE
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    • v.26 no.3
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    • pp.401-407
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    • 2022
  • Recently, image processing technology for autonomous driving by recognizing objects and lanes through camera images to realize autonomous vehicles is being studied. Haze reduces the visibility of images captured by the camera and causes malfunctions of autonomous vehicles. To solve this, it is necessary to apply the haze removal function that can be processed in real time to the camera. Therefore, in this paper, the fog removal method of Sim with excellent performance is implemented with hardware capable of real-time processing. The proposed hardware was designed using Verilog HDL, and FPGA was implemented by setting Xilinx's xc7z045-2ffg900 as the target device. As a result of logic synthesis using Xilinx Vivado program, it has a maximum operating frequency of 276.932MHz and a maximum processing speed of 31.279fps in a 4K (4096×2160) high-resolution environment, thus satisfying the real-time processing standard.

Improved Row Processor of DWT using a Lifting-Based Scheme (Lifting-Based Scheme을 이용한 DWT의 개선된 ROW Processor 구현)

  • 최영철;정영식;장영조
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.883-886
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    • 2003
  • 본 논문에서는 Lifting-Based Scheme을 이용한 DWT(Discrete Wavelet Transform) 의 개선된 행 처리기의 구조를 제안 하였다. 제안된 행 처리기는 3개의 Adder 와 2개의 shifter를 사용 하였고 dual-port RAM을 사용하여 파이프 라인 구조를 취하여 각 클럭마다 열처리기에서 사용할 데이터를 발생 한다. 이러한 행 처리기의 파이프 라인 구조를 개선하여 Adder를 줄이고 행 처리기의 이용률을 최대로 하여 하드웨어의 공간적 비용 절감 효과를 가져 왔다. 제안된 구조는 Verilog를 사용하여 RTL설계를 한뒤 시뮬레이션으로 그 동작을 확인 하였다.

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