• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.37-43
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• 2009

The new still image compression standard JPEG2000 is consisted of DWT and EBCOT. In this paper, proposed and designed new algorithm in efficient EBCOT. BPC based on the contort. Proposed BPC Algorithm is forecasted coding pass using Sigstage, column, mpass value. BAC design apply 4-pipeline stage. EBCOT designed using Verilog HDL. Verification and Synthesis using Xillinx FPGA technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.49-54
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• 2005

This paper proposes the low power MDCT algorithm for precise FV with minimum size of sub-window in mobile phone. Proposed algerian uses the coefficient at the middle of whole result process requiring the least number of calculations, since it has a good characteristic when used as standard of the FV and needs minimum amount of operation. In addition, using the DCT result related to the middle frequency makes the characteristic of FV more superior because it suppresses the impulsive noise and difference of focus values is larger than any others. The proposed algorithm is implemented using Verilog HDL and verified using Excalibur-ARM board.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1387-1394
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• 2011

In this paper, a low-area symbol timing offset synchronization structure for WLAN Modem is proposed. Using CSD(Canonic Signed Digit) coefficients and CSS(Common Sub-expression Sharing) technique for the filter implementation, efficient structure for multiplication block can be obtained. Function simulation for proposed structure is done by using the preamble with timing offset. Through Verilog-HDL coding and synthesis, it is shown that the proposed symbol timing offset synchronization structure can be implemented with low-area semiconductor.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.59-62
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• 2003

The purpose of this paper is to present how to implement Segment_LCD display using SoC design. The SoC design is achieved by using an ARM_based Excalibur device. The Excalibur device offers an outstanding embedded development platform with ARM922T and FPA. The design in the Excailbur device uses the embedded AR띤 Processor core and the AMBA high-performance bus (AHH) to write to a memory-mapped slave peripheral in the FPGA portion of the device. Here, Segment_LCD is one kind of memory-mapped slave peripherals. In order to Implement the Segment_LCD display based on SoC design, four steps are fellowed. At first, IP modules are made by using Verilog HDL. Secondly, the ARM processor of the Excalibur is programmed using C in ADS (ARM Developer Suite). And in the third step, the whole system is simulated and verified. At last, modules are downloaded to SoCMaster kit. Both Quartus II software and ModelSim5.5e software are the key software tools during the design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1052-1057
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• 2006

The implement the adaptive partial response maximum likelihood (PRML) detector with tilt analyzer for asymmetric high-density optical storage system. For the estimation of disc tilt, we exploit spc patterns in each data frame. Because of using the ROM table to renew the coefficients of equalizer and reference values of branches, the complexity of the hardware is reduced. The proposed PRML has been designed and verified by VerilogHDL and synthesized by the Synopsys Design Compiler with Hynix $0.35{\mu}m$ STD cell library. In the result, the total gate count is 35K, and the maximum operating frequency is 140MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.69-74
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• 2009

We propose the novel Hybrid bus arbitration policy that prevents starvation phenomenon presented in fixed priority and effectively assigns a priority to each master by mixing fixed priority and round-robin arbitration policies. The proposed arbitration policy and the others were implemented through Verilog and mapped the design into Hynix 0.18um technology and compared about gate count and design overhead. In the results of performance analysis, we confirm that our proposed policy outperforms the others in the aspect of design complexity, timing margin, bus utilization, starvation prevention, request cycle and so on.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.681-684
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• 2008

Bluetooth baseband performs FEC (forward error check) at the interface of transmitter and receiver modem. Well-designed FEC means directly the efficiency of retransmission of the data payload therefore design optimization is very important. In this paper, we designed a optimal 1/3, 2/3 type of FEC. 1/3 FEC. which performs 3 times customary repetition was designed for packet header, and 2/3 FEC was designed for data packets with (15, 10) reduced hamming code. The proposed hardware FEC block was described and verified using Verilog HDL and later to be automatically synthesized. The synthesized FEC block operated at 40Mhz normal clock speed of the target baseband microcontroller.

• Smart Media Journal
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• v.4 no.4
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• pp.39-46
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• 2015

This paper describes hardware implementation of the encryption block of the '128 bit block cipher LEA' among various lightweight encryption algorithms for IoT (Internet of Things) security. Round function blocks and key-schedule blocks are designed by parallel circuits for high throughput. The encryption blocks support secret-key of 128 bits, and are designed by FSM method and 24/n stage(n=1, 2, 3, 4, 8, 12) pipeline methods. The LEA-128 encryption blocks are modeled using Verilog-HDL and implemented on FPGA, and according to the synthesis results, minimum area and maximum throughput are provided.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.1
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• pp.146-150
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• 2009

Nowdays needs the new still image compression standard. JPEG2000 has been developed. JPEG2000 divide DWT and EBCOT. EBCOT is consisted of Bit Plane Coding and ARithmetic Coding algorithm. In this paper, we proposed BPC algorithm that is efficient context-based generation. Proposed BPC Algorithm forecasted coding pass using SigStage, column, mpass value. BPC designed using Verilog HDL. H/W implemenates using Xillinx FPGA technology.