• 말소리와 음성과학
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• 제9권2호
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• pp.85-94
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• 2017

Conventional speaker verification systems using time delay neural network, identity vector and probabilistic linear discriminant analysis (TDNN-Ivector-PLDA) are known to be very effective for verifying long-duration speech utterances. However, when test utterances are of short duration, duration mismatch between enrollment and test utterances significantly degrades the performance of TDNN-Ivector-PLDA systems. To compensate for the I-vector mismatch between long and short utterances, this paper proposes to use probabilistic linear discriminant analysis (PLDA) model adaptation with augmented data. A PLDA model is trained on vast amount of speech data, most of which have long duration. Then, the PLDA model is adapted with the I-vectors obtained from short-utterance data which are augmented by using vocal tract length perturbation (VTLP). In computer experiments using the NIST SRE 2008 database, the proposed method is shown to achieve significantly better performance than the conventional TDNN-Ivector-PLDA systems when there exists duration mismatch between enrollment and test utterances.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 추계학술대회 논문집
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• pp.430-435
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• 2008

Hyundai-Rotem Company has designed and manufactured Light Railway Vehicle (LRV) according to the Urban Rail Transit Code, which applies to urban railway vehicles in Korea. The Urban Rail Transit Code specifies the loads, for which vehicle bodies shall be capable of withstanding, identifies how material data shall be used and presents the principles to be used for design verification by analysis and test. The structural design of railway vehicle bodies depends on the loads they are subjected to and the characteristics of the materials they are manufactured from. Therefore Hyundai-Rotem Company has carried out Finite Element Analysis (FEA) and has performed load tests on the vehicle body according to the Urban Rail Transit Code. This research contains the results obtained by the analysis and the load tests. The analysis was carried out using I-DEAS Master Series 12 and load test were carried out using specially designed test jigs and equipment are used for the load tests.

• 자동차안전학회지
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• 제16권2호
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• pp.60-66
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• 2024

Computer simulation significantly reduces the high costs associated with actual crash tests and is expanding due to its ability to analyze various test results quantitatively that are difficult to measure in real tests. Research on evaluation technologies is limited according to the finite element analysis, which aims to replace structural verification testing. In this study, considerations for virtual crash tests were derived, and the validity of the zero-energy mode (hourglass mode) was analyzed as part of the considerations for validating the results of vehicle crash simulations. The study reflects on the considerations for virtual crash tests and the variation in hourglass coefficient values affects the occurrence of the hourglass mode. As the hourglass coefficient changes, the maximum hourglass energy reaches over 5% of the maximum internal energy, necessitating a conservative review. A comprehensive study of the maximum hourglass energy is required, considering additional analysis results for various models and collision conditions.

• 대한영양사협회학술지
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• 제18권3호
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• pp.222-233
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• 2012

The purpose of this study was the improvement and modification of the HACCP verification checklist in school foodservices. For this, the HACCP verification checklist was modified on the basis of an existing school foodservice format. The modified checklist was composed of 28 items, including CCPs (critical control points), microbial test, and other components of the HACCP system than CCPs. To confirm the suitability of the modified checklist, comparisons were made based on the microbiological quality of cooked foods, utensils, and number of aerial microbes in the working area. In this study, the applicability of the modified checklist was determined by focusing on cooked squid with seasoned fresh vegetables (Ojingeochaesomoochim). The following results were obtained from 14 schools in Changwon. The checklist scores for maintaining hot foods over $60^{\circ}C$ or serving within 2 hours, microbial tests of drinking water, food contact surfaces and cooking utensils, monitoring tools, and usage of suitable sanitizers were 2 points each (The possible highest score is 2 points). On the contrary, the checklist score for microbial test of cooked foods was the lowest of all the items. The correlation coefficient (r) between the improved checklist and microbiological quality of cooked foods was 0.699 (P<0.01), whereas that between the improved checklist and microbiological quality of cooking utensils was 0.612 (P<0.05). The correlation coefficient between the improved checklist and aerial plate count in the working area was -0.556 (P<0.05). Our results indicate the potential possibility of using the HACCP verification checklist in school foodservices.

• 한국추진공학회:학술대회논문집
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• 한국추진공학회 2011년도 제37회 추계학술대회논문집
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• pp.654-657
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• 2011

한국형 달탐사 계획을 성공적으로 수행하기 위해 한국항공우주연구원에서는 지상 모델을 이용한 핵심기술 확보 및 성능 검증을 수행하기 위한 연구를 진행 중에 있다. 추진시스템의 핵심 기술을 확보하기 위해 핵심 구성품인 추진제 탱크에 대한 국산화 개발을 진행하고 있으며 이를 이용하여 최종적인 추진시스템의 제작/시험을 수행할 예정이다. 본 논문에서는 개발 중인 추진제 탱크의 외부 구조물 가공 결과 및 수압 시험 결과를 소개하였다.

• 한국항공우주학회지
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• 제40권7호
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• pp.623-628
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• 2012

임무탑재장비 체계는 한국형 기동헬기의 임무 수행을 위해 전자장비 구성품들을 통합한 항공전자 체계다. 자체진단 시험은 숙련된 요원, 특수 시험장비의 필요성을 감소시키주며 체계의 정비를 위한 비가동 시간을 줄여준다. 갈수록 복잡성이 증가하고 있는 항공전자 장비에 대한 자체진단 시험 기능의 필요성이 더욱 커지고 있다. 본 논문은 한국형 기동헬기 항공전자 체계에 구현한 자체진단 시험 설계 및 입증에 대해 설명한다.

• 한국콘텐츠학회논문지
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• 제4권2호
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• pp.61-67
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• 2004

인터넷을 위시한 정보통신의 발달과 초고속정보통신망의 구축에 따라 라우터, 허브, 브리지 등의 네트워크를 구축하는 데에 소요되는 네트워크 장비들에 대한 수요가 급격히 증가하고 있다. 이에 비해 고도의 기술을 필요로 하는 네트워크장비 시장에서 이제까지 외국산 장비들이 국내시장을 석권해왔다. 근래에 와서 네트워크 장비의 중요성과 시장성을 인식하여 국내에서도 각종 네트워크 장비들을 개발/생산하고 있으나 아직은 외국산 장비의 기술과 경쟁하기에는 지극히 미흡한 단계에 있는 실정이다. 이렇게 개발/생산된 장비들이 실제 망에 설치되기 위해서는 그 기능과 성능을 인증 받아야 하는데 이를 위해서 외국 시험기관를 이용할 경우에는 많은 경비와 시간이 소요된다. 국내 네트워크 장비 업체가 세계적인 경쟁력을 갖기 위해서는 네트워크 장비 분야의 기술력을 높여야 할 뿐만 아니라, 이런 장비의 개발로 시험인증에 드는 비용과 시간을 절약하는 것이 중요하다. 따라서, 본 연구에서는 이러한 점을 고려하여 우리나라의 네트워크 장비 시장 현황과 네트워크 장비 시험 현황을 조사하고 우리나라 환경에 적합하고 국내 제품이 세계적인 경쟁력을 갖출 수 있도록, 효율적으로 네트워크 장비를 시험할 수 있는 추진 방향을 제시하고자 한다.

• 전기학회논문지
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• 제63권6호
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• pp.758-763
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• 2014

These days, the advantages of DC power system are consistently stand out in korea that was a small power loss and high stability. Needs of DC power transmission technology is focused In the midst of a smart grid and environment friendly generation technology boom that is needed for next generation technology. Researches and businesses for HVDC(High Voltage Direct Current) system has been began. But, Needs of HVDC equipment and system commissioning technology are not on the rise until now. In particular, South Korea's HVDC technology is after the foot runner of advanced country and company. In addition, There is no experience for equipment verification and commissioning technology. And Experts of HVDC are rare. Who has been fully understood hardware and system as a whole, and identified all the equipment's characteristic. Recently, Academia and industry are recognized a needs of HVDC technology. But it does not received a recognition of technical value. In this paper, introduce issues when we apply the IEEE's verification method for HVDC system, especially DC current measurement system, DC CT(Direct Current Transformer), among the HVDC equipments. And Proposes remedial methods on the issue in order to recognize the necessity that was HVDC equipments's verification and commissioning technology research should be focused on.

• 한국정보전자통신기술학회논문지
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• 제10권2호
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• pp.176-183
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• 2017

대용량 EEPROM 메모리를 테스트하는 경우 erase time과 program time이 많이 걸리는 문제가 있다. 또한 신뢰성 테스트를 진행하면서 각 스텝마다 EEPROM 셀의 문턱전압 VT를 테스트할 필요가 있다. 본 논문에서는 512kb EEPROM 셀 검증용 모듈 회로를 설계하였으며, negative VTE를 갖는 split gate EEPROM의 VT 측정을 위한 CG(Control Gate) 구동회로를 제안하였다. 제안된 CG 구동회로는 erase VT를 측정하기 위해 -3V~0V의 negative 전압이 인가될 수 있도록 asymmetric isolated HV (High-Voltage) NMOS 소자를 사용하였다. 그리고 test time reduction 모드에서는 even page, odd page, chip 단위로 erase나 program 수행이 가능하도록 회로를 설계하므로 512Kb EEPROM 전체 메모리를 erase하거나 program할 때 시간을 even page와 odd page를 이용하는 경우는 4ms, chip 전체로 하는 경우는 2ms로 테스트 시간을 줄일 수 있었다.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 2002년도 춘계공동학술발표회요약집
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• pp.135.1-135
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• 2002