• 제목/요약/키워드: Verification of design

검색결과 2,957건 처리시간 0.03초

5경간 강박스교의 내진성능검토 (Earthquake Resistant Verification of a 5-Span Steel Box Girder Bridge)

  • 국승규
    • 한국지진공학회:학술대회논문집
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    • 한국지진공학회 1998년도 추계 학술발표회 논문집 Proceedings of EESK Conference-Spring 1998
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    • pp.103-112
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    • 1998
  • The earthquake resistant design for roadway bridges introduced in 1992 is conducted according to the "Standard Specification for Roadway Bridges", Division V, Seismic Design and the first revision of the Standard was done in 1996. However, dur to different concepts of the earthquake resistant design from those of the other designs, the provisions given in the Standard are still not applied appropriately. In this paper the verification of the earthquake resistant capacity of a bridge with typical configurations, 5-span steel box girder bridge, is carried out based on the application rules of the present Standard in order to provide clear understandings about the earthquake resistant verification and the earthquake resistant design as well.n as well.

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KASS 시스템 통합 및 검증 활동 (Integration, Verification, Qualification Activities for KASS System)

  • 정환호;손민혁;이병석
    • 한국항행학회논문지
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    • 제27권6호
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    • pp.782-787
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    • 2023
  • KASS (korea augmentation satellite system) 시스템 통합 및 검증(IVQ; integration, verification, qualification) 활동은 시스템 및 하위시스템 요구사항 검증 활동으로 IART(inspection, analysis, review of design, test) 기반으로 상세설계 (CDR; critical design review) 이후 하위시스템 공장수락시험 (FAT; factory acceptance test)부터 현장수락시험 (SAT; site acceptance test) 그리고 시스템 통합 검증 시험 (TRR; test readiness review) 까지 수행하였다. FAT 단계의 활동은 개발된 장비를 테스트 플랫폼에 설치하고 각 장비별 인터페이스 검증과 통합운영국(KCS; kass control station)과의 연동시험을 통해 성능을 검증하였다. SAT 단계의 활동은 FAT 단계에서 검증된 KRS (kass reference station), KPS (kass processing station), KUS (kass uplink station), KCS를 운영 현장에 설치하고 검증하는 단계이며 개발 일정 및 여건을 고려하여 3단계로 구분하여 수행하였다. TRR 단계의 활동은 항공위성1호기에서 방송되는 SBAS (satellite based augmentation system) 메시지를 이용하여 SAT을 통해 검증된 장비를 FAT 단계에 수행했던 시험 항목과 추가 시험 항목 검증을 통해 전체 시스템에 대한 성능 검증을 완료하였다.

전원부하분석을 통한 무인항공기 전기시스템 설계 및 검증 (Design and Verification of Electrical System for Unmanned Aerial Vehicle through Electrical Load Power Analysis)

  • 우희채
    • 한국군사과학기술학회지
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    • 제21권5호
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    • pp.675-683
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    • 2018
  • In this paper, we have proposed a design and verification methods of electrical system and power loads for unmaned aeriel vehicles(UAVs) through electrical load analysis. In order to meet a UAV system requirement and electrical system specifications, we have designed an electrical power system for efficient power supply and distribution and have theoretically analyzed the power loads according to the power consumption and power bus design of UAV. Using electrical system rig, the designed electrical power system has been experimentally verified. Also, we have performed several flight tests to verify the UAV electrical system and power loads. It is concluded that the proposed design and verification method of electrical system for UAV system.

계층성을 이용한 VHDL 행위 수준에서의 설계 오류 탐색 알고리듬 (Design Error Searching Algorithm in VHDL Behavioral-level using Hierarchy)

  • 윤성욱;정현권김진주김동욱
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.1013-1016
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    • 1998
  • A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.

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임베디드 프로세서와 재구성 가능한 구조를 이용한 SoC 테스트와 검증의 통합 (Integration of SoC Test and Verification Using Embedded Processor and Reconfigurable Architecture)

  • 김남섭;조원경
    • 대한전자공학회논문지SD
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    • 제43권7호
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    • pp.38-49
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    • 2006
  • 본 논문에서는 SoC를 검증 및 테스트하기 위한 새로운 개념의 칩을 제안하고 이를 SwToC(System with Test on a Chip)라 명명한다. SwToC는 SoC의 임베디드 프로세서에 재구성 가능한 로직을 추가하여 칩의 물리적인 결함을 테스트할 수 있을 뿐만 아니라 기존의 기법으로는 수행이 어려웠던 테스트 단계에서의 디자인 검증이 가능하도록 한 칩을 말한다. 제안한 개념의 칩은 고속 검증이 가능하며 테스트를 위해 많은 비용이 소모되는 ATE 가 불필요한 장점을 갖고 있다. 제안한 칩의 디자인 검증 및 테스트 기능을 평가하기 위하여 임베디드 프로세서가 내장된 상용 FPGA를 이용하여 SwToC를 구현하였으며, 구현 결과 제안한 칩의 실현 가능성을 확인하였고 적은 비용의 단말기를 통한 테스트가 가능함은 물론 기존의 검증기법에 비해 고속 검증이 가능함을 확인하였다.

Feasibility study of a novel hash algorithm-based neutron activation analysis system for arms control treaty verification

  • Xiao-Suo He;Yao-Dong Dai;Xiao-Tao He;Qing-Hua He
    • Nuclear Engineering and Technology
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    • 제56권4호
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    • pp.1330-1338
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    • 2024
  • Information on isotopic composition and geometric structure is necessary for identifying a true warhead. Nevertheless, such classified information should be protected physically or electronically. With a novel Hash encryption algorithm, this paper presents a Monte Carlo-based design of a neutron activation analysis verification module. The verification module employs a thermal neutron source, a non-uniform mask (physically encrypting information about isotopic composition and geometric structure), a gamma detector array, and a Hash encryption algorithm (for electronic encryption). In the physical field, a non-uniform mask is designed to distort the characteristic gamma rays emitted by the inspected item. Furthermore, as part of the Hash algorithm, a key is introduced to encrypt the data and improve the system resolution through electronic design. In order to quantify the difference between items, Hamming distance is used, which allows data encryption and analysis simultaneously. Simulated inspections of simple objects are used to quantify system performance. It is demonstrated that the method retains superior resolution even with 1% noise level. And the performances of anti-statistical attack and anti-brute force cracking are evaluated and found to be very excellent. The verification method lays a solid foundation for nuclear disarmament verification in the upcoming era.

활용성을 고려한 BIM 설계 오류 검증시스템 개발 (Development of an Verification System for Enhancing BIM Design Base on Usability)

  • 양동석
    • 토지주택연구
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    • 제8권1호
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    • pp.23-29
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    • 2017
  • The BIM design is expected to expand to the domestic and overseas construction industries, depending on the effect of construction productivity and quality improvement. However, with the obligation of Public Procurement Service to design the BIM design, it includes a design error and the problem of utilization of 3D design by choosing a simple 2D to 3D remodelling method that can not be modelled in 3D modeling or use of the construction and maintenance phases. The results reviewed by BIM design results were largely underutilized and were not even performed with the verification of the error. In order to resolve this, one must develop the check system that secures the quality of BIM design and ensure that the reliability of BIM results are available. In this study, it is designed to develop a program that can automatically verify the design of the BIM design results such as violation of the rules of the BIM design, design flaws, and improve the usability of the BIM design. In particular, this programs were developed not only to identify programmes that were not commercially available, but also to validate drawings in low-light computer environments. The developed program(LH-BIM) store the information of attribute extracted from the Revit file(ArchiCAD, IFC file included) in the integrated DB. This provides the ability to freely lookup the features and properties of drawings delivered exclusively by the LH-BIM Program without using the Revit tools. By doing so, it was possible to resolve the difficulties of using traditional commercial programs and to ensure that they operate only with traditional PC performance. Further, the results of the various BIM software can be readily validated, which can be solved the conversion process error of IFC in the case of SMC. Additionally, the developed program has the ability to automatically check the error and design criteria of the drawings, as well as the ability to calculate the area estimation. These functions allow businesses to apply simple and easy tasks to operate tasks of BIM modelling. The developed system(LH-BIM) carried out a verification test by reviewing the review of the BIM Design model of the Korea Land & Housing Corporation. It is hoped that the verification system will not only be able to achieve the Quality of BIM design, but also contribute to the expansion of BIM and future construction BIM.

우선순위 규칙을 적용한 BIM 기반 설계검증 성과 분석 (BIM-based Design Verification Performance Analysis with Priority Rules Applied)

  • 허승하;심재형;함남혁;김재준
    • 한국BIM학회 논문집
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    • 제11권3호
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    • pp.1-11
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    • 2021
  • BIM is one of the means of reducing the economic loss caused by design errors. These features of BIM have led to increased use of BIM. With the increasing use of BIM, several studies have been conducted to analyze the performance of BIM. As the importance of BIM staff is emphasized in the performance analysis of BIM, the human resource allocation of BIM staff can become an important research issue. However, there are few studies to measure the workforce effectiveness of BIM staff. Ham et al (2020) measured BIM workforce efficiency using FCFS queue model rules. Since design errors can have different effects on the project depending on the type, there are design errors that must be dealt with first. Therefore, in this study, a priority queue was used to solve design errors with high priority first. The performance of BIM-based design verification was analyzed by quantitatively analyzing the performance of BIM staff when the priority rule was applied to the design error processing sequence.

CISC micro controller 설계 및 검증 과정에 관한 연구 (Design of CISC Micro Controller and Study on Verification Step)

  • 김경수;박주성
    • 대한전자공학회논문지SD
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    • 제41권6호
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    • pp.71-80
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    • 2004
  • 본 논문은 8비트 마이크로 컨트롤러인 8051과의 호환성을 가진 16비트 마이크로 컨트롤러의 설계 및 검증 과정에 대해서 다루고 있다. 설계 디자인의 동작을 확인하기 위해 명령어별 검증과 명령어 조합에 의해 생성된 다양한 형태의 명령어 셋을 검증했다. 또한 다양한 형태의 명령어를 보다 효율적으로 검증하기 위한 방법을 제시한다. IMA-ADPCM, SOLA 등의 응용 프로그램의 검증을 통해서 설계 디자인의 동작을 확인하였다. 최종적으로 Xilinx FPGA(XCV1000-560C)를 이용한 보드 구현을 통해서 명령어 및 응용 프로그램 등의 동작을 검증했다. 타겟 컨트롤러인 8비트 마이크로 컨트롤러, 8051과의 호환성 및 성능비교를 통해서 널리 사용 중인 8051을 대체 할 수 있고 보다 나은 성능을 발휘할 수 있다는 것을 보인다.

심해저 채광로봇 기술개발을 위한 Verification & Validation의 적용 (Application of Verification & Validation for deepsea mining robot technology development)

  • 성기영;조수길;오재원;여태경;홍섭;김형우
    • 한국산업융합학회 논문집
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    • 제22권6호
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    • pp.689-702
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    • 2019
  • This paper deals with the verification of the functions about mining robot, which is the system for developing deep seabed resources by applying V&V(verification and validation). In order to overcome water pressure of 500 bar and to travel on soft ground, and to operate in deep sea environment with bad conditions, it is necessary to develop a robot that can satisfy various deepsea conditions. A mining robot has been developed based on simulation based design and Multidisciplinary design optimization. In order to verify the developed robot, lab test and real sea test should be performed for various marine environment conditions. There are too many requirements to consider, such as space, time, cost, personnel, and environment to do performance test. So it is costly and time consuming for developing robot. In order to solve this problems, V&V technique was applied to mining robot. The stages of mining robot design, fabrication and commission were verified.