• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.17-24
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• 2014

In this paper, we implement and evaluate the performance of a vector-based rasterization algorithm for 3D graphics by using a SIMD (single instruction multiple data) many-core processor architecture. In addition, we evaluate the impact of a data-per-processing elements (DPE) ratio that is defined as the amount of data directly mapped to each processing element (PE) within many-core in terms of performance, energy efficiency, and area efficiency. For the experiment, we utilize seven different PE configurations by varying the DPE ratio (or the number PEs), which are implemented in the same 130 nm CMOS technology with a 500 MHz clock frequency. Experimental results indicate that the optimal PE configuration is achieved as the DPE ratio is in the range from 16,384 to 256 (or the number of PEs is in the range from 16 and 1,024), which meets the requirements of mobile devices in terms of the optimal performance and efficiency.

• Journal of Information Processing Systems
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• v.16 no.6
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• pp.1359-1371
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• 2020

In transmitting and receiving such a large amount of data, reliable data communication is crucial for normal operation of a device and to prevent abnormal operations caused by errors. Therefore, in this paper, it is assumed that an error correction code (ECC) that can detect and correct errors by itself is used in an environment where massive data is sequentially received. Because an embedded system has limited resources, such as a low-performance processor or a small memory, it requires efficient operation of applications. In this paper, we propose using an accelerated ECC-decoding technique with a graphics processing unit (GPU) built into the embedded system when receiving a large amount of data. In the matrix-vector multiplication that forms the Hamming code used as a function of the ECC operation, the matrix is expressed in compressed sparse row (CSR) format, and a sparse matrix-vector product is used. The multiplication operation is performed in the kernel of the GPU, and we also accelerate the Hamming code computation so that the ECC operation can be performed in parallel. The proposed technique is implemented with CUDA on a GPU-embedded target board, NVIDIA Jetson TX2, and compared with execution time of the CPU.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.56-64
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• 2004

In this research, design results of computer hardware which control solid motor movable nozzle thrust vector control(TVC) actuator for Korea Space Launch Vehicle I(KSLV-I) are described. TVC computer hardware is the equipment which has jobs for receiving control commands from Navigation Guidance Unit(NGU) and then actuating TVC actuator. Also, it has ability to communicate with other on board or ground equipments. Computer hardware has a digital signal processor as the main processor which is capable of high speed calculating ability of control algorithm, so it can have more stability, reliability and flexibility than the previous analog controller of KSR-III. Target board was designed for on board program development and then first prototype hardware was developed. Top level system design criteria, hardware configurations and ground support equipment of TVC computer system are described.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.6
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• pp.488-493
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• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.149-156
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• 2012

Support vector machines (SVMs) are well known for their pattern recognition capability, but proper care should be taken to alleviate their inherent implementation cost resulting from high computational intensity and memory requirement, especially in embedded systems where only limited resources are available. Since the memory requirement determined by the dimensionality and the number of support vectors is generally too high for a cache in embedded systems to accomodate, frequent accesses to the main memory occur inevitably whenever the cache is not able to provide requested data to the processor. These frequent accesses to the main memory result in overall performance degradation and increased energy consumption because a memory access typically takes longer and consumes more energy than a cache access or a register access. In this paper, we propose a technique that reduces the number of main memory accesses by optimizing the data access pattern of the SVM-based classifier in such a way that the temporal locality of the accesses increases, fully utilizing data loaded into the processor chip. With experiments, we confirm the enhancement made by the proposed technique in terms of the number of memory accesses, overall execution time, and energy consumption.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.985-993
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• 2008

This paper proposes a new DFIG(Doubly-Fed Induction Generator) system using matrix converter, which is very effectively used for interconnecting the wind power system to the power grid. The operation of proposed system was verified by computer simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was conformed by experimental works with a laboratory scaled-model of wind power system. The laboratory scaled-model was built using a motor-generator set with vector drive system, and a matrix converter with DSP(Digital Signal Processor). The operation of scaled-model was tested by modeling the specific variable-speed wind turbine using the real wind data in order to make the scaled-model simulate the real wind power system as close as possible. The simulation and experimental results confirm that matrix converter can be applied for the DFIG system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2291-2302
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• 1994

This paper shows the implementation and design of special processor for linearly shift knapsack public key cryptography system. We highten the density of existing knapsack vector and shift the vectors linearly in order to implement the structure of linearly shift knapsack system which has the stronger cryptosystem. As it needs the parallel processing at each path according to the characteristics of this system. we propose the pipelined parallel structure and implement this system into VLSL. Also we evaluate this system and compare with other systems. The processing speed of this system is 550kb/s when dimension is 100. It is possible to use this system at the place of requiring high speed security to enlarge the structure of it.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.10 no.2
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• pp.9-15
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• 2011

In order to develop a practical postprocessor for 5-axis machining, the general equations of numerically controlled (NC) data for 5-axis configurations with not only non-orthogonal rotary axes but also orthogonal rotary axes were exactly expressed by the inverse kinematics, and a Windows-based postprocessor written in Visual Basic was developed according to the proposed algorithm. The developed postprocessor is a general system that suitable for all kinds of 5-axis machine tool with orthogonal and non-orthogonal rotary axes. Through implementation of the developed postprocessor and verification by a cutting simulation and machining experiment, the effectiveness of the proposed algorithm is confirmed. Compatibility is improved by allowing exchange of data formats such as rotational tool center position (RTCP) controlled NC data, vector post NC data, and program object file (POF) cutter location (CL)data, and convenience is increased by adding the function of work-piece origin offset. Consequently, the technology of practical post-processor for 5-axis machining is developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1207-1212
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• 2011

This paper presents a study on the DSP(Digital Signal Processor) controller for the PBW(power-by-wire) system using BLDC(Brushless Direct Current) servo motor pump. The PBW hydraulic actuator was realized with hydraulic pump driven by BLDC servo motor, hydraulic cylinder and controller. This PBW system needs speed control of servo motor for linear thrust action of hydraulic cylinder. This paper implements a servo controller with vector control algorithm and MIN-MAX PWM technique. As CPU of a controller, TMS320F2812 DSP was adopted because it has PWM waveform generator, A/D converter, SPI(Serial Peripheral Interface) port and many input/output port etc.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.692-704
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• 2005

With the improvement of computer hardware, GPUs(Graphics Processor Units) have tremendous memory bandwidth and computation power. This leads GPUs to use in general purpose computation. Especially, GPU implementation of compute-intensive physics based simulations is actively studied. In the solution of differential equations which are base of physics simulations, tridiagonal matrix systems occur repeatedly by finite-difference approximation. From the point of view of physics based simulations, fast solution of tridiagonal matrix system is important research field. We propose a fast GPU implementation for the solution of tridiagonal matrix systems. In this paper, we implement the cyclic reduction(also known as odd-even reduction) algorithm which is a popular choice for vector processors. We obtained a considerable performance improvement for solving tridiagonal matrix systems over Thomas method and conjugate gradient method. Thomas method is well known as a method for solving tridiagonal matrix systems on CPU and conjugate gradient method has shown good results on GPU. We experimented our proposed method by applying it to heat conduction, advection-diffusion, and shallow water simulations. The results of these simulations have shown a remarkable performance of over 35 frame-per-second on the 1024x1024 grid.