• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1104-1114
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• 2007

Digital video compression technique has played an important role that enables efficient transmission and storage of multimedia data where bandwidth and storage space are limited. The new video coding standard, H.264/AVC, developed by Joint Video Team(JVT) significantly outperforms previous standards in compression performance. Especially, variable length code(VLC) plays a crucial pun in video and image compression applications. H.264/AVC standard adopted Context-based Adaptive Variable Length Coding(CAVLC) as the entropy coding method. CAVLC of H.264/AVC requires a large number of the memory accesses. This is a serious problem for applications such as DMB and video phone service because of the considerable amount of power that is consumed in accessing the memory. In order to overcome this problem in this paper, we propose a variable length technique that implements memory-free coeff_token, level, and run_before decoding based on arithmetic operations and using only 70% of the required memory at total_zero variable length decoding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.524-526
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• 1999

In the construction of successful fuzzy models and/or controllers for nonlinear systems, the identification of a good fuzzy inference system is an important yet difficult problem, which is traditionally accomplished by a time-consuming trial-and-error process. In this paper, we propose a systematic identification procedure for complex multi-input single-output nonlinear systems with DNA coding method. A DNA coding method is optimization algorithm based on biological DNA as conventional genetic algorithms(GAs) are. The strings in the DNA coding method are variable-length strings, while standard GAs work with a fixed-length coding scheme. the DNA coding method is well suited to learning because it allows a flexible representation of a fuzzy inference system. We also propose a new coding method fur applying the DNA coding method to the identification of fuzzy models. This coding scheme can effectively represent the zero-order Takagi-Sugeno(TS) fuzzy model. To acquire optimal TS fuzzy model with higher accuracy and economical size, we use the DNA coding method to optimize the parameters and the number of fuzzy inference system. In order to demonstrate the superiority and efficiency of the proposed scheme, we finally show its application to a Duffing-forced oscillation system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1485-1490
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• 2005

Variable length code is an integral component of many international standards on image and video compression currently. Context-based Adaptive Variable Length Coding(CAVLC) is adopted by the emerging JVT(also called H.264, and AVC in MPEG-4). In this paper, we design an architecture for CAVLC encoder, including a coeff_token encoder, level encoder, total_zeros encoder and run_before encoder. The designed CAVLC encoder can encode one syntax element in one clock cycle. As a result of implementation by Vertex-1000e of Xilinx, its operation frequency is 68MHz. Therefore, it is very suitable for video applications that require high throughput.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.281-285
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• 2000

This paper proposes context-based coding methods for variable length coding of inter-frame DCT coefficients. The proposed methods classify run-level symbols depending on the preceding coefficients. No extra overhead needs to be transmitted, since the information of the previously transmitted coefficients is used for classification. Two entropy coding methods, arithmetic coding and Huffman coding, are used for the proposed context-based coding. For Huffman coding, there is no complexity increase from the current standards by using the existing inter/intra VLC tables. Experimental results show that the proposed methods give ～ 19% bits gain and ～ 0.8 dB PSNR improvement for adaptive inter/intra VLC table selection, and ～ 37% bits gain and ～ 2.7dB PSNR improvement for arithmetic coding over the current standards, MPEG-4 and H.263. Also, the proposed methods obtain larger gain for small quantizaton parameters and the sequences with fast and complex motion. Therefore, for high quality video coding, the proposed methods have more advantage.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.1
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• pp.57-68
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• 2004

Although variable-length codes (VLCs) increase coding efficiency using the statistical characteristics of the source data, they have catastrophic effects from bit errors in noisy transmission environments. In order to overcome this problem with VLCs, reversible variable-length codes (RVLCS) have recently been proposed owing to their data recovering capability. RVLCS can be divided into two categories: symmetrical and asymmetrical RVLCs. Although the symmetrical RVLC has generally more overheads than the asymmetrical RVLC, it has some advantages of simpler design and more efficient memory usage. However, existing symmetrical RVLCs still have high complexity in their code design and some room for improvement in coding efficiency. In this paper, we propose a new algorithm for constructing a symmetrical RVLC from the optimal Huffman code table. The proposed algorithm has a simpler design process and also demonstrates improved performance in terms of the average codeword length relative to the existing symmetrical RVLC algorithms.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.12a
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• pp.383-386
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• 2002

In this paper, we investigated the pattern recognition performance of the numeric patterns (from 0 to 9) using DNA coding method. The pattern recognition performance of the DNA coding method is compared to the that of the GA(Genetic Algorithm). GA searches effectively an optimal solution via the artificial evolution of individual group of binary string using binary coding, while DNA coding method uses four-type bases denoted by A(Adenine), C(Cytosine), G(Guanine) and T(Thymine), The pattern recognition performance of GA and DNA coding method is evaluated by using the same genetic operators(crossover and mutation) and the crossover probability and mutation probability are set the same value to the both methods. The DNA coding method has better characteristics over genetic algorithms (GA). The reasons for this outstanding performance is multiple possible solution presentation in one string and variable solution string length.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1998.12a
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• pp.537-545
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• 1998

This paper is the research about a joint coding system of source and channel coding using VF(Variable-to-fixed length) arithmetic code and BCH code. We propose a VF arithmetic coding method with EDC( Error Detecting Capability) and a joint coding method in that the VF arithmetic coding method with EDC is combined with BCH code. By combining both the VF arithmetic code with EDC and BCH code. the proposed joint coding method corrects a source codeword with t-errors in decoding of BCH code and carries out a improvement of the EDC of a codeword with more than (t＋1)-errors in decoding of the VF arithmetic coding with EDC. We examine the performance of the proposed method in terms of compression ratio and EDC.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.72-80
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• 1998

A method is proposed for directional vector quantization using the wavelet packets. After partitioning the wavelet packet coefficients into 9 edges according to the corresponding directions, it encodes and transmits locally dominant edges. The directions of the edges are encoded with a variable length coding and conditional switching of codebooks, while the contents of them with the vector quantization followed by the variable length index coding. The proposed algorithm is superior to various conventional image coding algorithms in the sense of PSNR, which is relatively more significant at very low bit rate such as 0.1~0.3 bpp. As the proposed algorithm preserves the edges which is the most important for the human visual system, it also provides the reconstructed images of good subjective quality even at very low bit rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.108-111
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• 2008

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder engine for real time Full HD video compression. Since there are 384 data coefficients which are sum of 376 AC coefficient and 8 DC coefficient per one macroblock, 384 coefficient have to be processed per one macroblock in worst case for real time processing. We propose an novel architecture which includes parallel architecture and pipeline processing, and reduction "0" in AC/DC coefficient table. To verify the proposed architecture, we develop the reference C for CAVLC and verified the designed circuit with the test vector from reference C code.