• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.53-60
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• 2009

Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.309-315
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• 2010

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 Hz to 480 Hz, the midband gain programmable from 48.7 dB to 59.5 dB, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 nW in a 0.13 ${\mu}m$ CMOS process at the supply voltage of 0.7 V.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.6
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• pp.99-105
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• 2014

The performance improvement in MPEG-4 AVC is provided at the expense for higher computational complexity. Most of the complexity is caused by Inter prediction. To improve coding efficiency, some functions are added in H.264/MPEG-4 AVC, such as variable block size motion compensation, multi reference frame and quarter-pel motion compensation. A fast macroblock partition decision method is proposed in this paper. The macroblock size is efficiently determined by using the pixel value difference between encoding and the referred macroblock.

• Journal of Broadcast Engineering
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• v.12 no.2
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• pp.128-136
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• 2007

Since the multi-view video is a set of video sequences captured by multiple array cameras for the same three-dimensional scene, it can provide multiple viewpoint images using geometrical manipulation and intermediate view generation. Although multi-view video allows us to experience more realistic feeling with a wide range of images, the amount of data to be processed increases in proportion to the number of cameras. Therefore, we need to develop efficient coding methods. One of the possible approaches to multi-view video coding is to generate an intermediate image using view interpolation method and to use the interpolated image as an additional reference frame. The previous view interpolation method for multi-view video coding employs fixed size block matching over the pre-determined disparity search range. However, if the disparity search range is not proper, disparity error may occur. In this paper, we propose an efficient view interpolation method using initial disparity estimation, variable block-based estimation, and pixel-level estimation using adjusted search ranges. In addition, we propose a multi-view video coding method based on H.264/AVC to exploit the intermediate image. Intermediate images have been improved about $1{\sim}4dB$ using the proposed method compared to the previous view interpolation method, and the coding efficiency have been improved about 0.5 dB compared to the reference model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.58-65
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• 2007

As multimedia portable devices become popular, the amount of computation for processing data including video compression has significantly increased. Various researches for low power consumption of the mobile devices and real time processing have been reported. Motion Estimation is responsible for 67% of H.264 encoder complexity. In this research, a new circuit is designed for motion estimation. The new circuit uses motion prediction based on approximate SAD, Alternative Row Scan (ARS), DAU, and FDVS algorithms. Our new method can reduce the amount of computation by 75% when compared to multi-frame motion estimation suggested in JM8.2. Furthermore, optimal number and size of reference frame blocks are determined to reduce computation without affecting the PSNR. The proposed Motion Estimation method has been verified by using the hardware and software Co-Simulation with iPROVE. It can process 30 CIF frames/sec at 50MHz.

• Progress in Medical Physics
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• v.5 no.1
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• pp.87-99
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• 1994

Purpose : The determination of electron beam output factor was investigated from individual applicator for various energy of ML-15MDX linear accelerator. The output factor of electron beam was extended from square to rectangular field in individual applicator size through with a least-square fit to a polynomial expression. Materials : In this experiments. the measurement of output was obtained from 2${\times}$cm$^2$ to 20${\times}$20cm$^2$ of field size in different applicator size for 4 to 15 MaV electron beam energy. The output factor was defined as the ratio of maximum dose output on the central axis of the field of individual applicator size to that of a given field size. Applicator factors were derived from comparing with the output dose of reference field size 10${\times}$10cm$^2$. The thickness of block was specially designed as 10mm in thickness of Lipowitz metal for field shaping in all electron energy. Two types of output curves are included as output factors versus side of square fields and that of variable side length for X and Y in one-dimensional to compare the expected values to that of experiments. Results : Expected output factors of rectangular which was derived from that of square fields in individual applicator size from 2${\times}$2cm$^2$ to 20${\times}$20cm$^2$ in different electron energy was very closed to that of experimental measurements within 2% uncertainty. However 1D method showed a 3% discrepancy in small rectangular field for low energy electron beam. Conclusion : Emperical non-linear polynomial regressions of square root and 1D method were performed to determin the output factor in various field size and electron energy. The expected output of electron beam of square root method for square field and 1D method for rectangular field were very closed to that of measurement in all selected electron beam energy.

• The Transactions of the Korea Information Processing Society
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• v.4 no.12
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• pp.3159-3174
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• 1997

This paper reports a research to develop a methodology and a tool for understanding of very large and complex real-time software. The methodology and the tool mostly developed by the author are called the Architecture-based Real-time Software Understanding (ARSU) and the Software Re/reverse-engineering Environment (SRE) respectively. Due to size and complexity, it is commonly very hard to understand the software during reengineering process. However the research facilitates scalable re/reverse-engineering of such real-time software based on the architecture of the software in three-dimensional perspectives: structural, functional, and behavioral views. Firstly, the structural view reveals the overall architecture, specification (outline), and the algorithm (detail) views of the software, based on hierarchically organized parent-chi1d relationship. The basic building block of the architecture is a software Unit (SWU), generated by user-defined criteria. The architecture facilitates navigation of the software in top-down or bottom-up way. It captures the specification and algorithm views at different levels of abstraction. It also shows the functional and the behavioral information at these levels. Secondly, the functional view includes graphs of data/control flow, input/output, definition/use, variable/reference, etc. Each feature of the view contains different kind of functionality of the software. Thirdly, the behavioral view includes state diagrams, interleaved event lists, etc. This view shows the dynamic properties or the software at runtime. Beside these views, there are a number of other documents: capabilities, interfaces, comments, code, etc. One of the most powerful characteristics of this approach is the capability of abstracting and exploding these dimensional information in the architecture through navigation. These capabilities establish the foundation for scalable and modular understanding of the software. This approach allows engineers to extract reusable components from the software during reengineering process.