• Journal of the Korean Vacuum Society
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• v.8 no.4B
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• pp.536-540
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• 1999

We have developed a refractory WNx self-aligned gate GaAs metal-semiconductor field-effect transistor(MESFET) using $SiO_2$ side-wall process. The MESFET hasa fully ion-implanted, planar, symmetric self-alignment structure, and it is quite suitable for integration. The uniform trans-conductance of 354nS/mm up to Vgs=+0.6V and the saturation current of 171mA/mm were obtained. As high as 43GHz of cut-off frequency hs been realized without any de-embedding of parasitic effects. The refractory WNx self-aligned gate GaAs MESFET technology is one of the most promising candidates for realizing linear power amplifier ICs and multifunction monolithic ICs for use in the digital mobile communication systems such as hand-held phone(HHP), personal communication system (PCS) and wireless local loop(WLL).

• Journal of Korean Society of Industrial and Systems Engineering
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• v.35 no.2
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• pp.196-203
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• 2012

When manufacturing die casting mold, generally, the casting layout design should be considered based on the relation between injection system, casting condition, gate system, and cooling system. Also, the extent or the location of product defects were differentiated according to the various relations of the above conditions. High-qualified products can be manufactured as those defects are controled by the proper modifications or the changes of die casting mold with the conditions. In this research, the proper manufacturing method was derived intensively for reducing the defect of the internal porosity of steering wheel housing which is very complicated to achieve a good mold design. The method was also derived for minimizing and for guaranteeing the product quality through the analysis of the casting problem and the deduction of alternative plans.

• Journal of Korea Foundry Society
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• v.27 no.4
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• pp.153-158
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• 2007

Molten metal flow in vacuum die casting was characterized by a numerical analysis. The VOF method was used to simulate the filling behaviors of molten metal during filling process. The various vacuum degrees of no vacuum(760 mmHg), 650, 500, 250 and 60mmHg were artificially applied in cavity. And the filling behaviors of molten metal with the applied vacuum conditions were simulated and compared with those of experiment. The results showed that molten metal was partially filled into cavity when vacuum was applied and the filling length of molten metal in cavity was increased with increasing applied reduced pressure in cavity. Also, the simulated filling behaviors of molten metal were apparently similar to those of experiment, indicating the numerical analysis developed in this study was highly effective. Through the result of fluid flow simulation, both relation equations of filling length and filling velocity with the variation of pressure conditions in cavity were calculated respectively and the internal gas contents of casting was significantly reduced by the modification of vacuum gate system.

• Applied Science and Convergence Technology
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• v.23 no.4
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• pp.192-199
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• 2014

The electronic property of graphene was investigated by hydrazine treatment. Hydrazine ($N_2H_4$) highly increases electron concentrations and up-shifts Fermi level of graphene based on significant shift of Dirac point to the negative gate voltage. We have observed contact resistance and channel length dependent mobility of graphene in the back-gated device after hydrazine monohydrate treatment and continuously monitored electrical characteristics under Nitrogen or air exposure. The contact resistance increases with hydrazine-treated and subsequent Nitrogen-exposed devices and reduces down in successive Air-exposed device to the similar level of pristine one. The channel conductance curve as a function of gate voltage in hole conduction regime keeps analogous value and shape even after Nitrogen/Air exposure specially whereas, in electron conduction regime change rate of conductance along with the level of conductance with gate voltage are decreased. Hydrazine could be utilized as the highly effective donor without degradation of mobility but the stability issue to be solved for future application.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.38 no.1
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• pp.44-51
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• 2015

When manufacturing die casting mold, generally, the casting layout design should be considered based on the relations of injection system, casting condition, gate system, and cooling system. According to the various relations of the conditions, the location of product defects was differentiated. High-qualified products can be manufactured as those defects are controlled by the proper modifications of die casting mold with keeping the same conditions. In this research, Computer Aided Engineering (CAE) simulation was performed with the several layout designs in order to optimize the casting layout design of an automotive part (Housing). In order to apply them into the production die-casting mold, the simulation results were analyzed and compared carefully. With the filling process, internal porosities caused by air entrapments were predicted and also compared with the modification of the gate system and overflow. With the solidification analysis, internal porosities occurring during the solidification process were predicted and also compared with the modified gate system. The simulation results were also applied into the production die-casting mold in order to compare the results and verify them with the real casting samples.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.118-118
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• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.208-213
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• 1998

Silicidation of the Co/Ti/Si bilayer system in which Ti is used as epitaxy promoter for $CoSi_2$has recently received much attention. The Co/Ti bilayer on the spacer oxide of gate electrode must be thermally stable at high temperatures for a salicide transistor to be fabricated successfully. In the $SiO_2$substrate was rapid-thermal annealed. The Sheet resistances of the Co/Ti bilayer increased substantially after annealing at $600^{\circ}C$, which is due to the agglomeration of the Co layer to reduce the interface energy between the Co layer and the $SiO_2$substrate. In the bilayer system insulating Ti oxide stoichiometric Ti oxide and silicide were not found after annealing.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.27-27
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• 1998

진공기술의 응용과 진공환경의 이용은 더 이상 논하지 않더라도 산업 전반에 그 충요성이 점점 더 커가고 있다. 이러한 여건에도 불구하고 진공율 이용하는 system 개밟의 국산화는 수 입하는 system으$\mid$ 수에 비하여 절대적으로 부족하며, 또한 개발하는 system의 자동화는 거의 이 루어지지 않고 있으며, 자동화된 진공판련 system은 거의 대부분 수입에 의흔하고 있다. 실험 실 규모에서부터 System올 하나하나 개밭하고, 이톨 자동화하는 노력과 일이 진행됨다면 산업 응용에 있어서도 자연스럽게 자동화된 system으$\mid$ 개발이 이루어 질 것이다 .. system 자동화는 상 품수명의 단축과 이에 따른 다품종 소량을 요구하는 시장수요에 대응하고, 인력절감과 고풀짙 화로 생산성 향상의 요구에 대응하기 위하여 필요하다. 본 연 구에 서 는 e-beam evaporator로 evaporation하면 서 ion beam으로 assist하여 thin film율 제 작하는 IBAD vacuum system율 싫 계 및 제 작하고[1,2], PLC[3,떼톨 이 용하여 system 자동화톨 하였다 .. thin film 제작 process는 먼저 기본 진공상태로 만뚫고 난 뒤, e-beam evaporator로 e evaporation하면서 ion beam source로 assist하여 substrate 011 thin film율 제조한다 226;. thin film올 제 조하면서 thickness monitor로 sample의 thickness rate톨 control 하고, sample의 균얼성과 밀착 성을 고려하여 substrate톨 rotation 및 heating 할 수 있도록 싫계, 제작하였다. 양질의 박막올 제조하기 위해서 진공환경이 좋은 상태로 제공되어야 한다. 이톨 위하여 oil free operation 0 I 가 능한 dry pump와 turbo molecular pump로 고진공 배기 하였다. 진공도의 흑점은 thermal effect 툴 고려하여 cold cathode ion gauge률 사용하였고, intro chamber와 main chamber 사이에는 g gate valve톨 설치하여 벌도로 운용되도록 하였다. 이러한 process를 박막의 두께, 진공도, 시 간, 온도, 공정 동의 조건올 기훈으로 자동화한 것이다. 또한 정전과 단수에 대한 interlock 기능 도 고려하였다.하였다.