• Journal of the Korean Vacuum Society
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• v.6 no.3
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• pp.287-292
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• 1997

This study was tried to form the silica waveguide using high density plasma. Plasma characteristics have been investigated as a function of etch parameters using a single Langmuir probe and optical emission spectroscopy(OES). As etch parameters, $CF_4/CHF_3$ ratio, bias power, and source power were chosen as main variables. The oxide etch characteristics of inductively coupled plasma(ICP) dry etcher such as the etch rate, etch profile, and surface roughness were investigated s a function of etch parameters. On the basis of these results, the core pattern of the wave guide composed of $SiO_2-P_2O_5$ was formed. It was confirmed that the etch rate of $SiO_2-P_2O_5$ core layer was 380 nm/min and the aluminum selectivity to oxide, that is, mask layer was approximately 30:1. The SEM images showed vertical etched profiles and minimal loss of pattern width.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.139-141
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• 2005

It is possble to study charge transfer property which is caused by height variation because we can see the organic materials barrier height and STM tip by organic materials energy band gap. Here, we investigated the negative differential resistance(NDR) and charge transfer property of self-assembled 4,4-Di(ethynylphenyl)-2'-nitro-1-(thioacetyl)benzene, which has been well known as a conducting molecule. Self-assembly monolayers(SAMs) were prepared on Au(111), which had been thermally deposited onto pre-treatment($H_{2}SO_{4}:H_{2}O_{2}$=3:1) Si. The Au substrate was exposed to a 1 mM/l solution of 1-dodecanethiol in ethanol for 24 hours to form a monolayer. After thorough rinsing the sample, it was exposed to a $0.1{\mu}M/1$ solution of 4,4-Di(ethynylphenyl)-2'-nitro-1-(thioacetyl)benzene in dimethylformamide(DMF) for 30 min and kept in the dark during immersion to avoid photo-oxidation. After the assembly, the samples were removed from the solutions, rinsed thoroughly with methanol, acetone, and $CH_{2}Cl_{2}$, and finally blown dry with $N_2$. Under these conditions, we measured electrical properties of self-assembly monolayers(SAMs) using ultra high vacuum scanning tunneling microscopy(UHV-STM). The applied voltages were from -1.50 V to -1.20 V with 298 K temperature. The vacuum condition is $6{\times}10^{-8}$ Torr. As a result, we found that NDR and charge transfer property by a little change of height when the voltage is applied between STM tip and electrode.

• Proceedings of the Korean Society For Composite Materials Conference
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• 2003.04a
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• pp.196-201
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• 2003

When the structures are used in cold regions, the mechanical properties and dimension stability of the blade will be changed. The proposal of this study is to test the durability of the structures in cold regions. It is necessary to select the most comfortable materials and fabrication processes for more stable structures in cold regions. To select the most comfortable materials and processes, the static strength has to know through the tensile static tests at the severe condition as cold regions. First, the tensile static specimens made by RIM (Resin injection molding) process & vacuum bagging process with reinforcement materials and resin. Tensile static tests were carried out on three laminate lay-ups (carbon prepreg, carbon fiber dry fabric) at different test temperature($24^{\circ}C$, $-30^{\circ}C$), determining properties such as the mechanical strength, stiffness and strain to failure. At different test temperature, in order to test the tensile strengths of these specimens used the low temperature chamber. Next, the results of this test were compared with each other. Finally, the most comfortable materials and fabrication processes can select based on these results. The results show the changes in the static behavior of three laminate lay-ups at different test temperatures. At low temperatures, the static strengths are higher than the ones at room temperature.

• Journal of the Korean Vacuum Society
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• v.17 no.2
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• pp.113-116
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• 2008

As the integration in semiconductor display develops, semiconductor process becomes multilayer. In order to form several layer patterns, etching process which uses photoresistor (PR) must be performed in multilayer process. Repeated etching processes which take long time and PR residue cause mortal problems in semiconductor. To overcome such problems, we studied about the solution which eliminates PR effectively by using normal dry and wet etching method using plasma activated PR strip solvent in liquid condition. At first, we simulate the device which activates the plasma and make sure whether gas flow in device is uniform or not. Under activated plasma, etching effect is elevated. This improvement reduces etching time as well as display production time of semiconductor process. Generally, increasing etching process increases environmental hazards. Reducing etching process can save the etchant and protect environment as well.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.366-370
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• 2007

Nano-scopic holes which are distributed densely and uniformly were fabricated on $SiO_2$ surface. Self-assembling resists were used to produce a layer of uniformly distributed parallel poly methyl methacrylate (PMMA) cylinders in a polystyrene (PS) matrix. The PMMA cylinders were degraded and removed by acetic acid rinsing. Subsequently, PS nanotemplates were fabricated. The patterned holes of PS template were approximately $8{\sim}30\;nm$ wide, 40 nm deep, and 60 nm apart. The porous PS template was used as a dry etching mask to transfer the pattern of PS template into the silicon oxide thin film during reactive ion etching (RIE) process. The sizes of the patterned holes on $SiO_2$ layer were $9{\sim}33\;nm$. After pattern transfer by RIE, uniformly distributed holes of which size were in the range of $6{\sim}22\;nm$ were fabricated on Si substrate. Sizes of the patterned holes were controllable by PMMA molecular weight.

• Journal of the Korean Vacuum Society
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• v.21 no.6
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• pp.354-361
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• 2012

The organic memory device was made by the plasma polymerization method which was not the dry process but the wet process. The memory device consist of the styrene and MMA monomer as the insulating layer, MMA monomer as the tunneling layer and Au thin film as the memory layer which was fabricated by thermal evaporation method. The I-V characteristics of fabricated memory device got the hysteresis voltage of 27 V at 40/-40 V double sweep measuring conditions. At this time, the optimized structure was 7 nm of Au thin film as floating gate, 400 nm of styrene thin film as insulating layer and 30 nm of MMA thin film as tunneling layer. Therefore we got the charge trapping characteristics by the hysteresis voltage. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make devices by using styrene thin film rather than Au thin film.

• Journal of the Korean Vacuum Society
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• v.8 no.1
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• pp.63-69
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• 1999

The characteristic parameters of high density plasma source (Helical Resonator) have been measured with Langmuir probe to get the plasma density electron temperature, ion current density, etc. Optical emission spectra of Si and SiCl have been analyzed in $Cl_2$$/poly-Si system to elucidate etching mechanism. In this system, the main reaction to remove silicon atoms on the surface is proceeding mostly through chemical reaction, not pure physical reaction. The emission intensity of SiCl (chemical etching product) increases much faster than Si (pure physical etching product) with increasing the concentration of impurities (P). This is due to the electron transfer from substrate to the surface via Si-Cl bond. As a result, Si-Cl bond becomes more ionic and mobile, therefore the Cl-containing etchant forms $SiCl_x$ with surface more easily. Consequently, for the removal of Si atom from poly silicon surface, the chemical etching is more favorable than physical etching with increasing P concentrations.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.281-281
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• 2011

산업 환경에서 친환경 및 에너지효율성을 중요한 조건이 되면서 고효율성 및 다기능을 가진 재료에 대한 연구가 활발히 진행 되고 있다. 특히 Al-Ti-N 코팅은 이미 경도 측면에서 우수 하여 고속 공구 부품에 널리 사용되고 있고 최근에 Al-TiN에서 Si 첨가는 40GPa이상의 고경도와 1000도 이상의 산화온도를 지닌 나노 혼합물 코팅을 형성 시키는 것으로 알려져 있다. 본 연구에서 Al-Ti에 Si, Cu, Cr 을 첨가하였을 때 코팅을 형성하였을 때 바뀌는 물성 변화을 확인하였다. 이러한 연구를 위해 Al-Ti 합금 조성 중 가장 우수한 것으로 알려진 60:40으로 타겟을 만들어 스퍼터 장비를 이용해 코팅을 형성하여 기초 실험을 진행하였다. 그 근거로 하여 3원계인 Si, Cu, Cr 을 첨가하여 각각의 단일 타겟으로 만들고 코팅을 형성하였다. 타겟과 코팅의 성분이 동일한지 확인하기 위해 EPMA분석을 하였고 그 결과 오차 범위 내에 동일한 것으로 확인하였다. 또 내산화성 테스트를 위해 400도에서 1000도로 가열된 대기 중에 코팅 층을 1시간씩 노출시키는 공정을 통해 확인하였고 내식성 테스트는 SUS 304계열 위에 코팅을 하여 Potentiodynamic polarization scan 장비로 비교해 보았다. 표면경도는 3원계 코팅인 경우 질소비율이 증가할수록 30GPa ~ 35GPa까지 증가하였고 XRD 분석 결과와 비교 시 (111), (200) peak가 명확할수록 경도 값이 높은 것으로 확인하였다. 마모테스트 결과 3원계인 코팅 층이 dry상태에서 감소하는 경향을 보였다. 특히 0,26까지 감소한 Si 을 첨가한 코팅 층은 H/E지수도 좋아 마모트랙의 길이도 짧아 우수한 것으로 알 수 있었다. 이런 결과에서 보듯 3원소 이상 첨가 시 특성변화가 차이가 있다는 것을 알 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.499-499
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• 2011

Silicon nanowires (Si NWs) have been extensively studied for nanoelectronics owing to their unique optical and electrical properties different from those of bulk silicon. For the development of Si NW devices, better understanding of oxidation behavior in Si NWs would be an important issue. For example, it is widely known that atomic scale roughness at the dielectric (SiOx)/channel (Si) interface can significantly affect the device performance in the nano-scale devices. However, the oxidation process at the atomic-scale is still unknown because of its complexity. In the present work, we investigated the oxidation behavior of Si NW in atomic scale by simulating the dry oxidation process using a reactive molecular dynamics simulation technique. We focused on the residual stress evolution during oxidation to understand the stress effect on oxidation behavior of Si NWs having two different diameters, 5 nm and 10 nm. We calculated the charge distribution according to the oxidation time for 5 and 10 nm Si NWs. Judging from this data, it was observed that the surface oxide layer started to form before it is fully oxidized, i.e., the active diffusion of oxygen in the surface oxide layer. However, it is well-known that the oxide layer formation on the Si NWs results in a compressive stress on the surface which may retard the oxygen diffusion. We focused on the stress evolution of Si NWs during the oxidation process. Since the surface oxidation results in the volume expansion of the outer shell, it shows a compressive stress along the oxide layer. Interestingly, the stress for the 10 nm Si NW exhibits larger compressive stress than that of 5 nm Si NW. The difference of stress level between 5 an 10 anm Si NWs is approximately 1 or 2 GPa. Consequently, the diameter of Si NWs could be a significant factor to determine the self-limiting oxidation behavior of Si NWs when the diameter was very small.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.469-469
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• 2011

고효율 염료감응형 태양전지(DSSC, Dye-Sensitized Solar Cell)의 구현을 위해서 유용한 방법중 하나는 정렬된 기공 (pore)을 $TiO_2$막 내에 형성시키는 것이다. 메조포러스 (mesoporous) $TiO_2$막은 dip coating이나 spin coating과 같은 방법으로 주로 증착되고 있으며, P123이나 F127과 같은 amphiphilic triblock copolymer를 메조포러스 구조를 만들기 위한 뼈대로 사용하고 있다. 또한, 이렇게 생성된 구조에서 amphiphilic triblock copolymer는 열처리 공정을 통하여 쉽게 제거될 수 있다. 고효율 태양전지를 구현하는 또 다른 방법으로는 패턴 된 기판을 사용하는 것이다. 패턴 된 기판은 빛의 반사를 억제하여 흡수율을 높이는 역할을 한다. 그러나 패턴 된 기판 위에서 메조포러스 $TiO_2$막의 형성에 관한 연구는 부족한 실정이다. 본 연구에서는 spin coating 방법으로 패턴 된 Si (111) 기판 위에 메조포러스 $TiO_2$를 성장하고 그 미세구조를 분석하였다. 패턴 된 기판은 nanosphere lithography(NSL) 법으로 mask를 증착한 후 건식 식각 (dry etching) 공정을 통해서 제작되었으며, 마스크와 불순물 등 은 초음파 세척 등으로 제거되었다. 메조포러스 $TiO_2$막은 1-propanol, P123, titanium isopropoxide와 HCl을 섞어 만든 용액으로 1 cm${\times}$1 cm 기판 위에 3000 rpm과 4000 rpm으로 각각 증착하였으며, 5일 동안 4도에서 에이징한 후 350도에서 3시간 열처리하였다. 이렇게 형성한 메조포러스 막의 형상과 미세구조적 특성이 주사전자현미경(SEM, scanning electron microscope), X-선 회절(XRD, X-ray diffraction) 등을 이용하여 연구되었다. 특히, 증착 조건에 따른 메조포러스 $TiO_2$박막의 형성 기구에 관한 고찰이 진행되었다. 나아가, $TiO_2$박막과 패턴 사이에 형성되는 계면 구조에 관한 연구를 투과전자현미경을 이용하여 진행하였다.